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review.coreboot.org / coreboot / 40cb3fe94dacfba0b146aae2be9c03c0a0ddb691 / src / soc / intel / cannonlake / romstage
  1. b15946d soc/intel: Add max memory speed into dimm info by Eric Lai · 1 year, 2 months ago
  2. 7cba1c4 treewide: Remove duplicated include <device/pci.h> by Elyes Haouas · 1 year, 7 months ago
  3. 6be82a4 soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill by David Milosevic · 1 year, 10 months ago
  4. 0b92aa6 soc/intel: Rename heci_init to cse_init by Subrata Banik · 2 years, 3 months ago
  5. 8ba9410 soc/intel/cannonlake: Hook up FSP hyper-threading setting to option API by Felix Singer · 2 years, 8 months ago
  6. 7c2f57a soc/intel/cnl: Enable CSE FW sync for CSE LITE SKU by Matt DeVillier · 2 years, 6 months ago
  7. 74b85f2 soc/intel/cannonlake: Add PcieRpHotPlug config to FSP-M by Matt DeVillier · 2 years, 7 months ago
  8. 91c077f ChromeOS: Fix <vc/google/chromeos/chromeos.h> by Kyösti Mälkki · 2 years, 10 months ago
  9. 929b65a soc/intel/cannonlake: Merge soc_memory_init_params() into its caller by Felix Singer · 3 years, 4 months ago
  10. b03e497 soc/intel/cannonlake/romstage: Reuse device pointer by Felix Singer · 3 years, 4 months ago
  11. 3993d38 soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD by Angel Pons · 3 years, 4 months ago
  12. 53496e6 soc/intel: Drop `romstage_pch_init()` function by Angel Pons · 3 years, 6 months ago
  13. d456f65 {soc,vc,mb}/intel: Drop support for Cannon Lake SoC by Felix Singer · 3 years, 8 months ago
  14. 53b99a8 soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num() by Nick Vaccaro · 3 years, 11 months ago
  15. 0ed02d0 mb, soc: change mainboard_get_dram_part_num() prototype by Nick Vaccaro · 3 years, 11 months ago
  16. 490546f soc/intel: rename get_prmrr_size by Michael Niewöhner · 4 years ago
  17. a91c919 soc/intel/cannonlake: Set FSP-M UPD Heci1BarAddress by Sridhar Siricilla · 4 years ago
  18. c25c1eb src: Update bare access to BOOL CONFIG_ vals to CONFIG() by Martin Roth · 4 years, 1 month ago
  19. 03ed5bf soc/intel/cannonlake: Move tco_configure to bootblock by Tim Wawrzynczak · 4 years, 1 month ago
  20. c4b7027 src: Remove leading blank lines from SPDX header by Elyes HAOUAS · 4 years, 3 months ago
  21. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
  22. c49d7a3 src/: Replace GPL boilerplate with SPDX headers by Patrick Georgi · 4 years, 3 months ago
  23. e01054d soc/intel/cannonlake: Add DisableHeciRetry to config by Christian Walter · 4 years, 4 months ago
  24. b2f8ce7 soc/intel/cannonlake: Steal no memory for disabled IGD by Christian Walter · 4 years, 5 months ago
  25. f5627e8 soc/intel/cannonlake: Use SPDX for GPL-2.0-only files by Angel Pons · 4 years, 4 months ago
  26. 1c6d8a9 soc: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
  27. c004857da soc/intel/cannonlake: Add chip config for SATA strength by Jamie Chen · 4 years, 7 months ago
  28. 33ff4cc soc/intel/cannonlake: Refactor pch_early_init() code by Usha P · 4 years, 9 months ago
  29. e1470ea soc/intel/cannonlake: Add chip config to override CPU flex ratio by Subrata Banik · 4 years, 9 months ago
  30. 7736bfc soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig by Michael Niewöhner · 4 years, 10 months ago
  31. 32d47eb soc/intel: Rename <intelblocks/chip.h> by Kyösti Mälkki · 4 years, 11 months ago
  32. 81100bf soc/intel: Move fill_postcar_frame to memmap.c by Kyösti Mälkki · 5 years ago
  33. 1799011 soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code by Subrata Banik · 5 years ago
  34. a7d2f29 intel/car: Use common TS_START_ROMSTAGE by Kyösti Mälkki · 5 years ago
  35. cd7a70f soc/intel: Use common romstage code by Kyösti Mälkki · 5 years ago
  36. a963acd arch/x86: Add <arch/romstage.h> by Kyösti Mälkki · 5 years ago
  37. 8950cfb soc/intel: Use config_of() by Kyösti Mälkki · 5 years ago
  38. 903b40a soc/intel: Replace uses of dev_find_slot() by Kyösti Mälkki · 5 years ago
  39. 6e2d0c1 arch/x86: Adjust size of postcar stack by Kyösti Mälkki · 5 years ago
  40. 1a86cda soc/intel: Provide SPD manufacturer ID and module type to SMBIOS by Duncan Laurie · 5 years ago
  41. 4821a0e soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE by Arthur Heymans · 5 years ago
  42. 2973d1e vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155 by Aamir Bohra · 5 years ago
  43. f972322 src/soc/intel/common/smbios: Add addtional infos to dimm_info by Christian Walter · 5 years ago
  44. 46340d0 soc/intel: Fill DIMM serial number from SPD by Duncan Laurie · 5 years ago
  45. 1159a16 soc/intel/cnl: Enable VT-d by John Zhao · 5 years ago
  46. c338507 soc/{amd,intel}/chip: Use local include for chip.h by Elyes HAOUAS · 5 years ago
  47. 3717256 soc/intel/cannonlake: Enable PlatformDebugConsent by Kconfig by Kane Chen · 5 years ago
  48. cd4fe0f src: include <assert.h> when appropriate by Elyes HAOUAS · 5 years ago
  49. 7f1a0e6 Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML" by Lijian Zhao · 5 years ago
  50. 250dfc0 soc/intel/cannonlake: Configure Vmx support using Kconfig by Ronak Kanabar · 5 years ago
  51. 41dad28 soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML by Subrata Banik · 5 years ago
  52. 68890b9 soc/intel/cannonlake: Update CPU Ratio base on MSR by Lijian Zhao · 5 years ago
  53. cf32fd1 soc/intel/common: Remove common chip config use_fsp_mp_init by Subrata Banik · 6 years ago
  54. bfe4a59 soc/intel/cannonlake: Pass coreboot debug interface info to FSP by Maulik V Vaghela · 5 years ago
  55. 5c19009 soc/intel/cannonlake: Allow mainboard to override DRAM part number by Furquan Shaikh · 5 years ago
  56. cd49cce coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) by Julius Werner · 5 years ago
  57. 5fe77af soc/intel/cannonlake: Move power_state functions to pmutil.c by V Sowmya · 5 years ago
  58. 13f6650 device/mmio.h: Add include file for MMIO ops by Kyösti Mälkki · 5 years ago
  59. 065857e arch/io.h: Drop unnecessary include by Kyösti Mälkki · 5 years ago
  60. 993f68a soc/intel: Add mem_rank info in SMBIOS by Francois Toguo · 6 years ago
  61. 7e8bad4 soc/intel/cannonlake: Don't use CAR_GLOBAL by Arthur Heymans · 6 years ago
  62. 6527b1a soc/intel/cannonlake: Add Whiskeylake SoC kconfig by Subrata Banik · 6 years ago
  63. 52b5b58 soc/intel/cannonlake: Disable CpuRatio and SaGv in recovery by Duncan Laurie · 6 years ago
  64. 7bc4dc5 soc/intel/common/block: Move tco common functions into block/smbus by Subrata Banik · 6 years ago
  65. 0bc3e3d soc/intel/cannonlake: Enable/Disable IPU based on devicetree switch by V Sowmya · 6 years ago
  66. 3da1b0d soc/intel/cannonlake: Fix chipset_power_state structure by Duncan Laurie · 6 years ago
  67. 3ef7449 soc/intel/cannonlake: Auto turn on HDA controller by Lijian Zhao · 6 years ago
  68. fd02ff0 soc/intel/cannonlake: Enable CPU flexible ratio by Lijian Zhao · 6 years ago
  69. 8a5283a src: Remove unneeded include <cbmem.h> by Elyes HAOUAS · 6 years ago
  70. 25b387a soc/intel/cannonlake: Remove SmbusEnable by Duncan Laurie · 6 years ago
  71. fe701ee soc/intel/cannonlake: Enable ISH from device by Lijian Zhao · 6 years ago
  72. 521e48c soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions by praveen hodagatta pranesh · 6 years ago
  73. e26c4a4 soc/intel/cannonlake: Add new cannon lake PCH-H support by praveen hodagatta pranesh · 6 years ago
  74. d44221f Move compiler.h to commonlib by Nico Huber · 6 years ago
  75. 742c6fe soc/intel/cannonlake: Move the FSP related callbacks to separate files by Rizwan Qureshi · 6 years ago
  76. 3cb0e27 soc/intel/common: add acpi_get_sleep_type to pmclib by Bora Guvendik · 6 years ago
  77. a57447d soc/intel/cannonlake: Move SkipMpInit config to FSPM by Lijian Zhao · 6 years ago
  78. 6ea6775 soc/{amd,intel}: Use postcar_frame_add_romcache() by Nico Huber · 6 years ago
  79. 9593e97 soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE) by Nico Huber · 6 years ago
  80. 6403167 compiler.h: add __weak macro by Aaron Durbin · 6 years ago
  81. 26be35a soc/intel/cannonlake: Set DISB after Dram init by Lijian Zhao · 6 years ago
  82. 91c8e23 soc/intel/cannonlake: Add VT-d and VMX programming by Lijian Zhao · 6 years ago
  83. 5268b76 src/soc: Fix various typos by Jonathan Neuschäfer · 7 years ago
  84. f1b1d92 intel/fsp: Update cannonlake fsp header by Lijian Zhao · 7 years ago
  85. e8e4329 soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17 by Subrata Banik · 7 years ago
  86. 1428f01 soc/intel/cannonlake: enable pch link in bootblock by Caveh Jalali · 7 years ago
  87. 9b50a57 soc/intel/cannonlake: Program DMI PCR settings by Lijian Zhao · 7 years ago
  88. 22d20d6 soc/intel/cannonlake: Tell FSPM UART port number by Lijian Zhao · 7 years ago
  89. 66b5acc soc/intel/cannonlake: remove duplicate power_state migration by Patrick Georgi · 7 years ago
  90. e7a1e7d soc/intel/cannonlake: Fix HECI error on reset by Lijian Zhao · 7 years ago
  91. c672043 soc/intel/cannonlake: Set platform Debug Probe Type by Lijian Zhao · 7 years ago
  92. 319e3b4 soc/intel/cannonlake: Create acpi_get_sleep_type() to get previous sleep state by Subrata Banik · 7 years ago
  93. ed3e6b8 soc/intel/cannonlake: Disable CPU ratio override by Lijian Zhao · 7 years ago
  94. 84c4987 soc/intel/cannonlake: Set IGD stolen memory size to 64MB by Subrata Banik · 7 years ago
  95. c8c741d soc/intel/cannonlake: Define Max PCIE Root Ports by Pratik Prajapati · 7 years ago
  96. 2678cd6 soc/intel/cannonlake: Add PrmrrSize and C6DRAM config by Subrata Banik · 7 years ago
  97. 9027e1b soc/intel/cannonlake: Init UPD params based on config by Pratik Prajapati · 7 years ago
  98. b3dfcb8 soc/intel/cannonlake: Enable common PMC code for CNL by Lijian Zhao · 7 years ago
  99. 8465a81 soc/intel/cannonlake: Add postcar stage support by Lijian Zhao · 7 years ago
  100. b4560cd Update files with no newline at the end by Martin Roth · 7 years ago