Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 40cb3fe94dacfba0b146aae2be9c03c0a0ddb691 / src / soc / intel / cannonlake / gpio_cnp_h.c
  1. 8a2c904 soc/intel/cannonlake: Use common gpio.h include by Dinesh Gehlot · 1 year, 7 months ago
  2. 624bf72 soc/intel/cannonlake: Fix GPIO reset mapping by Angel Pons · 1 year, 9 months ago
  3. 51f5ff6 soc/intel/{skl,cnl}: add NMI_{EN,STS} registers by Michael Niewöhner · 3 years, 9 months ago
  4. 5d1a328 soc/intel/cannonlake: add missing special function pads by Michael Niewöhner · 4 years ago
  5. 1c2b1b9 soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names by Michael Niewöhner · 4 years ago
  6. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
  7. ac95903 treewide: replace GPLv2 long form headers with SPDX header by Patrick Georgi · 4 years, 3 months ago
  8. 02363b5 treewide: Move "is part of the coreboot project" line in its own comment by Patrick Georgi · 4 years, 3 months ago
  9. 1c6d8a9 soc: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
  10. 76a8f9e soc/intel/cannonlake: Make use of gpio_pm_configure() by Subrata Banik · 5 years ago
  11. c126084 soc/intel: Add GPI interrupt config register offset info by Karthikeyan Ramasubramanian · 5 years ago
  12. 7471540 soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO by Rizwan Qureshi · 5 years ago
  13. 674c62b soc/intel/cannonlake: Fix CNL-H GPIO pin map by Duncan Laurie · 6 years ago
  14. 521e48c soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions by praveen hodagatta pranesh · 6 years ago