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review.coreboot.org / coreboot / 40cb3fe94dacfba0b146aae2be9c03c0a0ddb691 / src / soc / amd / stoneyridge / reset.c
  1. 3fe1ad1 soc/amd/stoneyridge/reset: use port and bit defines from cf9_reset.h by Felix Held · 3 years, 8 months ago
  2. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
  3. ae59387 soc/amd: Use SPDX for GPL-2.0-only files by Angel Pons · 4 years, 4 months ago
  4. 1c6d8a9 soc: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
  5. 69486ca soc/amd/common: Create AcpiMmio functionality from stoneyridge by Marshall Dawson · 5 years ago
  6. 73c1119 soc/amd: Implement common reset API by Nico Huber · 6 years ago
  7. 2e49cf12 amd/stoneyridge: Add warm reset detection by Marshall Dawson · 6 years ago
  8. e56189c pci: Move inline PCI functions to pci_ops.h by Patrick Rudolph · 6 years ago
  9. 48e44ee soc/amd/stoney: clean up and update reset.c by Martin Roth · 7 years ago
  10. dfeb1c4 stoneyridge: Rename hudson to southbridge by Marc Jones · 7 years ago
  11. 4e101ad soc/amd/stoneyridge: Fix most checkpatch errors by Marshall Dawson · 7 years ago
  12. 2448484 soc: Add AMD Stoney Ridge southbridge code by Marc Jones · 7 years ago