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review.coreboot.org / coreboot / 3fa80a9c6f44362e53d33d09da1875a42b98b30f / src / soc / intel / braswell / southcluster.c
  1. 3fa80a9 soc/intel/braswell: Put SERIRQ in quiet mode by Hannah Williams · 7 years ago
  2. 2cfdde7 soc/intel/braswell: Fix SPI write after FLOCKDN is set by Hannah Williams · 9 years ago
  3. d94cff6 soc/intel/braswell: Fix most of the issues detected by checkpatch by Lee Leahy · 7 years ago
  4. 1072e7d soc/intel/braswell: Add int to unsigned by Lee Leahy · 7 years ago
  5. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  6. 2bc9cee Braswell: Update the ACPI tables by Lee Leahy · 9 years ago
  7. 3247172 Braswell: Add Braswell SOC support by Lee Leahy · 9 years ago
  8. 25509ee Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  9. 77ff0b1 Braswell: Use Baytrail as Comparison Base by Lee Leahy · 9 years ago