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review.coreboot.org / coreboot / 3dbea29ee65c99ae09690765f20869b46464e66a / src / soc / intel / baytrail / xhci.c
  1. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  2. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  3. 18ea2d3 baytrail: Change all SoC headers to <soc/headername.h> system by Julius Werner · 10 years ago
  4. c9bf446 baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU by Kein Yuan · 10 years ago
  5. 9e94dbf ACPI: Get S3 resume state from romstage_handoff by Kyösti Mälkki · 10 years ago
  6. 51d787a rambi/baytrail: ACPI, GPIO, audio, misc updates by Shawn Nematbakhsh · 11 years ago
  7. 616f394 baytrail: utilize reg_script_run_on_dev() by Aaron Durbin · 11 years ago
  8. a90a59f5 baytrail: Fix XHCI problems and re-enable by Duncan Laurie · 11 years ago
  9. f81a91a baytrail: Add XHCI initialization by Duncan Laurie · 11 years ago