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3d0071bde363bbcd2ef3d68bac67400feced1778
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cpu
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intel
3d0071b
haswell: adjust CAR usage
by Aaron Durbin
· 12 years ago
7af2069
haswell: enable caching before SMM initialization
by Aaron Durbin
· 12 years ago
24614af
haswell: Clear correct number of MCA banks
by Aaron Durbin
· 12 years ago
a416bfe
haswell: move definition of CORE_THREAD_COUNT_MSR
by Aaron Durbin
· 12 years ago
29ffa54
haswell: Use SMM Modules
by Aaron Durbin
· 12 years ago
6dccedd
x86 intel: Add Firmware Interface Table support
by Aaron Durbin
· 12 years ago
51254049
haswell: Add ULT CPUID and updated microcode
by Duncan Laurie
· 12 years ago
dc278f8
haswell: Properly Guard Engergy Policy by CPUID
by Aaron Durbin
· 12 years ago
76c3700
haswell: Add initial support for Haswell platforms
by Aaron Durbin
· 12 years ago
5a22b14
Fix socket LGA775
by Kyösti Mälkki
· 11 years ago
a46a712
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
by Paul Menzel
· 11 years ago
0aa37c4
sconfig: rename lapic_cluster -> cpu_cluster
by Stefan Reinauer
· 12 years ago
8cc8468
Intel: Replace MSR 0xcd with MSR_FSB_FREQ
by Patrick Georgi
· 12 years ago
644e83b
speedstep: Deduplicate some MSR identifiers
by Patrick Georgi
· 12 years ago
223af0d
document Intel VMX locking behavior
by Mike Frysinger
· 12 years ago
6fe0cab
Extend CBFS to support arbitrary ROM source media.
by Hung-Te Lin
· 12 years ago
23f38cd
Get rid of drivers class
by Patrick Georgi
· 12 years ago
a42e2f4
Add spinlock to serialize Intel microcode updates
by Stefan Reinauer
· 12 years ago
455f4b4
Fix CONFIG_MAX_CPU set to 1 CPU build problem
by Stefan Reinauer
· 12 years ago
08067ba
ivybridge: Catch unknown CPU revisions
by Stefan Reinauer
· 12 years ago
f5a11aa
Initialize the VMX MSR
by Marc Jones
· 12 years ago
5986eda
Revert "Remove code that enables/disables VMX in coreboot on chromebooks."
by Marc Jones
· 12 years ago
bb9dff5
sandybridge: Correct reporting of cores and threads
by Stefan Reinauer
· 12 years ago
d16d576
Leave power control registers unlocked
by Sameer Nanda
· 12 years ago
68d7c7a
cpu/intel/model_1067x: Add proper c-state/p-state/thermal support
by Nico Huber
· 12 years ago
bf10bc3
intel/socket_BGA956: enable speedstep, CAR, MMX, SSE
by Patrick Georgi
· 12 years ago
a74af56
Overhaul speedstep code
by Nico Huber
· 12 years ago
252d39b
Fix some indentation flaws and break very long lines
by Nico Huber
· 12 years ago
ad874e3
Correct FSB reading in speedstep ACPI
by Nico Huber
· 12 years ago
41392df
Merge cpu/intel/acpi.h into cpu/intel/speedstep.h
by Nico Huber
· 12 years ago
bef3d34
Add support for socket LGA775
by Stefan Tauner
· 12 years ago
e5fe3ac
Fix typo in mPGA603 socket
by Kyösti Mälkki
· 12 years ago
0279036
Remove chip.h files without config structure
by Kyösti Mälkki
· 12 years ago
00b579a
buildsystem: Make CPU microcode updating more configurable
by Alexandru Gagniuc
· 12 years ago
0a78f91
Intel model_106cx: change CAR to HT-capable
by Kyösti Mälkki
· 12 years ago
fee73df
Auto-declare chip_operations
by Kyösti Mälkki
· 12 years ago
0db6820
Synchronize rdtsc instructions
by Stefan Reinauer
· 12 years ago
df0fbc7
Intel CPUs: Fix counting of CPU cores
by Kyösti Mälkki
· 12 years ago
51676b1
Revert "Use broadcast SIPI to startup siblings"
by Sven Schnelle
· 12 years ago
a2701c6
Revert "remove CONFIG_SERIAL_CPU_INIT"
by Sven Schnelle
· 12 years ago
5563211
CPU: Add option to set TCC activation offset
by Duncan Laurie
· 12 years ago
d6aca0b
ACPI: Add a method to notify OS to re-read _PPC
by Duncan Laurie
· 12 years ago
0eefa00
ACPI: Add function to write _PPC using NVS
by Duncan Laurie
· 12 years ago
0b7b7b6
Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs
by Stefan Reinauer
· 12 years ago
c65a36e
Enable Microcode in CBFS for all SandyBridge/IvyBridge systems
by Stefan Reinauer
· 12 years ago
c0f2cfb
Fix comment to reference IvyBridge, too
by Stefan Reinauer
· 12 years ago
6d29c73
Include SandyBridge Microcode when IvyBridge is enabled
by Stefan Reinauer
· 12 years ago
0aa5b09
Fix date output in Microcode update
by Stefan Reinauer
· 12 years ago
22935e1
CPU: Set flex ratio to nominal TDP ratio in bootblock
by Duncan Laurie
· 12 years ago
4e4320f
CPU: Update ivybridge PP1 current limit value
by Duncan Laurie
· 12 years ago
77dbbac
CPU: Add basic support for Nominal Configurable TDP
by Duncan Laurie
· 12 years ago
999e94c
Config changes to support microcode in CBFS
by Vadim Bendebury
· 12 years ago
39fea6e
Add microcode blob processing
by Vadim Bendebury
· 12 years ago
537b4e0
Add code to read Intel microcode from CBFS
by Vadim Bendebury
· 12 years ago
df0c822
Rename microcode include file to be model agnostic
by Vadim Bendebury
· 12 years ago
b38e0c3
Properly identify ACPI C3 states in _CST table.
by Duncan Laurie
· 12 years ago
305b19d
Remove code that enables/disables VMX in coreboot on chromebooks.
by Ronald G. Minnich
· 12 years ago
5458b9d
Intel cpus: Extend cache to cover complete Flash Device
by Kyösti Mälkki
· 12 years ago
ae7d6ef
Intel model_106cx: change CAR to model_6ex
by Kyösti Mälkki
· 12 years ago
4dcc573
Intel cpus: delete dead CAR code and whitespace fixes
by Kyösti Mälkki
· 12 years ago
c7fb2ae
Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR
by Kyösti Mälkki
· 12 years ago
78efc4c
remove CONFIG_SERIAL_CPU_INIT
by Sven Schnelle
· 12 years ago
042c146
Use broadcast SIPI to startup siblings
by Sven Schnelle
· 12 years ago
9ed1456
Intel CPUs: execute microcode update only once per core
by Kyösti Mälkki
· 12 years ago
edac28c
Enable Intel PECI on Model 6fx CPUs
by Sven Schnelle
· 12 years ago
bb31f3a
Drop config variable CPU_MODEL_INDEX
by Stefan Reinauer
· 12 years ago
e166782
Clean up #ifs
by Patrick Georgi
· 12 years ago
3b5a9ed
Fix register corruption during Intel Microcode update
by Stefan Reinauer
· 12 years ago
252111d
Don't include console.h in microcode.c when compiling with ROMCC
by Stefan Reinauer
· 12 years ago
c31384e
Fix up Sandybridge C state generation code
by Stefan Reinauer
· 12 years ago
4cc8c70
Rework ACPI CST table generation
by Stefan Reinauer
· 12 years ago
3110945
microcode: print date of microcode and unify output
by Stefan Reinauer
· 12 years ago
3f8989e
Revamp Intel microcode update code
by Stefan Reinauer
· 12 years ago
05e740f
Replace cache control magic numbers with symbols
by Patrick Georgi
· 12 years ago
f8c7c23
Fix support for RAM-less multi-processor init
by Kyösti Mälkki
· 12 years ago
5c55463
Add support for Intel Sandybridge CPU
by Stefan Reinauer
· 12 years ago
ea37a21
Add support for Intel Turbo Boost feature
by Stefan Reinauer
· 12 years ago
abdf15f
Apply cache-as-ram conditionally on socket mPGA604
by Kyösti Mälkki
· 12 years ago
819c7d4
Whitespace fixes
by Patrick Georgi
· 12 years ago
a860c68
Intel cpus: get MAXPHYADDR at runtime for new CAR
by Kyösti Mälkki
· 12 years ago
0078ceb
Intel cpus: add hyper-threading CPU support to new CAR
by Kyösti Mälkki
· 12 years ago
05d6ffb
Intel cpus: improve CPU compatibility of new CAR
by Kyösti Mälkki
· 13 years ago
f9d1a42
Intel cpus: apply some good programming practices in new CAR
by Kyösti Mälkki
· 12 years ago
325b92f
Intel cpus: cache actual size of the Flash ROM device
by Kyösti Mälkki
· 12 years ago
5a660ca
Intel cpus: copy model_6ex CAR code
by Kyösti Mälkki
· 12 years ago
8b28d50
Intel cpus: Fix deadlock on hyper-threading init
by Kyösti Mälkki
· 12 years ago
7a39446
Intel cpus: Include CAR from socket
by Kyösti Mälkki
· 13 years ago
53c1d20
Intel cpus: use CPU_PHYSMASK_HI define in CAR
by Kyösti Mälkki
· 13 years ago
adf105f
Intel model_106cx: Use symbolic names for MTRR bits
by Kyösti Mälkki
· 13 years ago
e13632a
Intel cpus: apply un-written naming rules
by Kyösti Mälkki
· 13 years ago
6d64ade
Add Intel Socket LGA771
by Sven Schnelle
· 13 years ago
adfbcb79
MTRR: get physical address size from CPUID
by Sven Schnelle
· 13 years ago
8d84613
ACPI: mark empty get_cst_entries() weak
by Sven Schnelle
· 13 years ago
784544b
Remove XIP_ROM_BASE
by Patrick Georgi
· 13 years ago
9438da3
Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9
by Rudolf Marek
· 13 years ago
914377e
Get rid of the old romstage-as-bootblock ROM layout
by Patrick Georgi
· 13 years ago
1da1046
Get rid of AUTO_XIP_ROM_BASE
by Patrick Georgi
· 13 years ago
5460097
SPEEDSTEP: write _CST tables
by Sven Schnelle
· 13 years ago
521d8c2
Activate older Xeon P4 microcodes
by Kyösti Mälkki
· 13 years ago
ac624a6
Crank up CPU speed on Intel Core and Core2 CPUs
by Patrick Georgi
· 13 years ago
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