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review.coreboot.org / coreboot / 35c0f439fc2bc29817d643a7629a4d2b79d6b903 / src / southbridge / intel / bd82x6x / lpc.c
  1. 35c0f43 Move nehalem/sandy/ivy to per-device acpi by Vladimir Serbinenko · 10 years ago
  2. 264d265 southbridge: Trivial - drop trailing blank lines at EOF by Edward O'Callaghan · 10 years ago
  3. c3ed886 intel boards: Use acpi_is_wakeup_s3() by Kyösti Mälkki · 10 years ago
  4. 9c50e6a Intel BD82x6x: LPC: Unify I/O APIC setup by Paul Menzel · 11 years ago
  5. 8c937c7 Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2 by Vladimir Serbinenko · 11 years ago
  6. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  7. a0bec17 Reserve bd82x6x LPC decode ranges in the resource allocator by Marc Jones · 12 years ago
  8. 800e950 ELOG: Log boot-time events found in southbridge by Duncan Laurie · 12 years ago
  9. e6f459c CougarPoint/PantherPoint: Add HM77 device ID to table by Kimarie Hoot · 12 years ago
  10. 3f6a4d7 Add specific power management init code for PantherPoint by Duncan Laurie · 12 years ago
  11. 9a380ab bd82x6x: Convert all PCI ID lists to new scheme by Stefan Reinauer · 12 years ago
  12. baae2d2 Add support for HM70 and NM70 LPC bridge by Stefan Reinauer · 12 years ago
  13. 95be1d6 Don't disable ACPI in the S3 resume path by Duncan Laurie · 12 years ago
  14. 459b777 add new LPC controller device ID value by Vadim Bendebury · 12 years ago
  15. 8e07382 Add support for Intel Panther Point PCH by Stefan Reinauer · 12 years ago