Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
328a694a3f2055c5e6a88ae51c9a8eefb61fd11c
/
src
/
northbridge
/
amd
/
amdmct
/
mct_ddr3
/
mct_d.c
328a694
AMD CPU and chipset fixes for compilation with gcc 4.6
by Stefan Reinauer
· 13 years ago
471f103
This patch sets max freq defaults for ddr2 and ddr3for fam10.
by Marc Jones
· 13 years ago
69436e1
Fix some settings fo AMD MCT. It is based on BIOS test suite.
by Zheng Bao
· 14 years ago
c3af12f
Trivial. Spell checking.
by Zheng Bao
· 14 years ago
7b1a3c3
Trivial. re-Indent the code.
by Zheng Bao
· 14 years ago
7cdf1ec
Obviously missing brackets.
by Xavi Drudis Ferran
· 14 years ago
951a0fe
Fix the typo. Field DisAutoRefresh is in DramTimngHi.
by Zheng Bao
· 14 years ago
e150e9a
Also improve boot time on AMD for the DDR3 code path. Fix a typo, too.
by Arne Georg Gleditsch
· 14 years ago
f7a999a
Trivial. Currently the max frequency is preset as 400Mhz. We need to set a
by Zheng Bao
· 14 years ago
08c92e0
AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.
by Kerry She
· 14 years ago
9fae99f
Get Byte65/66 for register manufacture ID code. RegMan1Present will
by Zheng Bao
· 14 years ago
108d30b
Trivial syntax correction of AMD mct_ddr3 dir.
by Kerry She
· 14 years ago
eb75f65
DDR3 support for AMD Fam10.
by Zheng Bao
· 14 years ago