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review.coreboot.org / coreboot / 2e17eaed1bfb2e6362790b4a7590c48c6602a8bf / src / soc / ucb / riscv
  1. fc5e6c6 soc/ucb/riscv: Place CBMEM at top of autodetected RAM by Jonathan Neuschäfer · 7 years ago
  2. 28a3ee6 soc/ucb/riscv: select BOOTBLOCK_CONSOLE by Jonathan Neuschäfer · 7 years ago
  3. 97dc986 arch/riscv: Move CBMEM into RAM by Jonathan Neuschäfer · 7 years ago
  4. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 8 years ago
  5. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  6. aae53ab kbuild: automatically include SOCs by Stefan Reinauer · 9 years ago
  7. ae98e83 CBMEM: Always use DYNAMIC_CBMEM by Kyösti Mälkki · 9 years ago
  8. 77b1655 vboot2: add verstage by Stefan Reinauer · 9 years ago
  9. aca2150 UCB RISCV: Switch to DYNAMIC_CBMEM by Kyösti Mälkki · 9 years ago
  10. e0e784a Add UCB RISCV support for architecture, soc, and emulation mainboard.. by Ronald G. Minnich · 9 years ago