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review.coreboot.org / coreboot / 2c423441c054d7a8c93cc814b9db5f8f7185bd0f / src / soc / intel / alderlake / chip.h
  1. a6d642f soc/intel/alderlake: Enable eMMC based on dev enabled by Krishna Prasad Bhat · 2 years, 6 months ago
  2. 7f8ab00 soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` config by Subrata Banik · 2 years, 6 months ago
  3. 38fcf40 soc/intel/alderlake: Add ADL-P 2+8+2 (28W) VR config by Curtis Chen · 2 years, 6 months ago
  4. 150fee6 soc/intel/alderlake: Update the ADL-P SKU parameters for VR domains by Curtis Chen · 2 years, 7 months ago
  5. fc69b9d soc/intel/alderlake: Add the CnviDdrRfim configuration by Ronak Kanabar · 2 years, 9 months ago
  6. 0c54461 soc/intel/alderlake: Add ADLP 4+4+2 power configurations by Curtis Chen · 2 years, 8 months ago
  7. c510346 soc/intel/alderlake: Add Acoustic noise mitigation UPDs by Wisley Chen · 2 years, 8 months ago
  8. d0cef2a soc/intel/alderlake: Enable Intel FIVR RFI settings by Wisley Chen · 2 years, 9 months ago
  9. d2fadda soc/intel: replace dt option PmTimerDisabled by Kconfig by Michael Niewöhner · 2 years, 10 months ago
  10. 4a48dbe src/soc/intel/alderlake: Add PsysPmax setting by Ryan Lin · 2 years, 10 months ago
  11. 21c431b soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU by Sumeet Pawnikar · 2 years, 10 months ago
  12. 697d6a8 soc/intel/alderlake: Add ADLP 242 power configurations by Tracy Wu · 2 years, 10 months ago
  13. ab0e081 soc/intel/alderlake: Add support for power cycle and SLP signal duration by Tim Wawrzynczak · 2 years, 10 months ago
  14. 8fcefd3 soc/intel/alderlake: add MaxDramSpeed config by Casper Chang · 2 years, 10 months ago
  15. e2b8f30 soc/intel/alderlake: Set LpmStateEnableMask UPD by Tim Wawrzynczak · 3 years ago
  16. eaf87a9 soc/intel/alderlake: set power limits dynamically for thermal by Sumeet Pawnikar · 2 years, 11 months ago
  17. d37a419 soc/intel/adl: Update power limits for ADL-M SKU by Sumeet Pawnikar · 3 years ago
  18. c6d7166 soc/intel/alderlake: Configure the SKU specific parameters for VR domains by V Sowmya · 3 years ago
  19. af42906 soc/intel/alderlake: Set max Pkg C-states to Auto by V Sowmya · 3 years, 1 month ago
  20. 418d37e soc/intel/alderlake: Add support to update the FIVR configs by V Sowmya · 3 years, 1 month ago
  21. 8a18bd8 soc/intel/alderlake/romstage: Update display UPDs based on InternalGfx by Subrata Banik · 3 years, 1 month ago
  22. aa49608 soc/intel/adl: Add SKU specific power limits support by Sumeet Pawnikar · 3 years, 2 months ago
  23. 8e7facf soc/intel/alderlake: mb/intel/sm: Add tcss code by Deepti Deshatty · 3 years, 2 months ago
  24. 633e0f2 soc/intel/alderlake: remove duplicate PL2 override by Sumeet R Pawnikar · 3 years, 2 months ago
  25. 50f8b4e soc/intel/alderlake: Add enum for HDA audio configuration by Sugnan Prabhu S · 3 years, 4 months ago
  26. c1c1ba5 soc/intel/alderlake and mb: Drop PchHdaAudioLink*Enable UPDs from chip.h by Furquan Shaikh · 3 years, 3 months ago
  27. 5d13e7f soc/intel/alderlake: Drop unused `PrmrrSize` from devicetree by Angel Pons · 3 years, 3 months ago
  28. 6935350 soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC by Maulik V Vaghela · 3 years, 3 months ago
  29. a67a322 soc/intel/alderlake: Drop unreferenced `InternalGfx` by Angel Pons · 3 years, 3 months ago
  30. 77298c6 soc/intel/alderlake: add processor power limits control support by Sumeet R Pawnikar · 3 years, 4 months ago
  31. bc1941f soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entry by Cliff Huang · 3 years, 5 months ago
  32. 98521c5 soc/intel: Retype `CnviBtAudioOffload` devicetree option by Angel Pons · 3 years, 5 months ago
  33. 5b302b2 soc/intel/alderlake: Refactor PCIE port config by Eric Lai · 3 years, 7 months ago
  34. cffc938 soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ by Subrata Banik · 3 years, 6 months ago
  35. 0b53d8b soc/intel/alderlake: Remove pch.h from SoC directory by Subrata Banik · 3 years, 6 months ago
  36. de2ab41 soc/intel/common: Move L1_substates_control to pcie_rp.h by Eric Lai · 3 years, 6 months ago
  37. 85144d9 soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs by Subrata Banik · 3 years, 6 months ago
  38. 43e93d7 soc/intel/alderlake: Drop unreferenced devicetree settings by Angel Pons · 3 years, 7 months ago
  39. a64b4f4 mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` by Michael Niewöhner · 3 years, 9 months ago
  40. 2871e0e soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage by Subrata Banik · 3 years, 10 months ago
  41. 292afef soc/intel/alderlake/romstage: Do initial SoC commit till romstage by Subrata Banik · 3 years, 10 months ago