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coreboot
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27d6299d51744bda549b7764b8fde909ad812e33
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src
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soc
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intel
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alderlake
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smihandler.c
5a49f3a
soc/intel/alderlake: Use PMC IPC to disable HECI1
by Subrata Banik
· 2 years, 7 months ago
32e0673
soc/intel/common/cse: Rework heci_disable function
by Subrata Banik
· 2 years, 7 months ago
7f8ab00
soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` config
by Subrata Banik
· 2 years, 8 months ago
7b7b33e
soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster
by Kane Chen
· 3 years, 4 months ago
2871e0e
soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage
by Subrata Banik
· 3 years, 11 months ago