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review.coreboot.org / coreboot / 27d6299d51744bda549b7764b8fde909ad812e33 / src / northbridge / intel
  1. 1ec5e74 Intel Sandybridge: add reserved memory as resources by Kyösti Mälkki · 12 years ago
  2. d4ee808 sandybridge: reinitialize usbdebug after MRC by Sven Schnelle · 12 years ago
  3. 6ff1d36 Intel and GFXUMA: fix MTRR and use uma_resource() by Kyösti Mälkki · 12 years ago
  4. 08ef498 Intel 82810 and 82830: always room for PCI memory by Kyösti Mälkki · 12 years ago
  5. b5f5652 Intel i945 and sch: no memory over 4GB by Kyösti Mälkki · 12 years ago
  6. efff733 Refactor driver structs by Patrick Georgi · 12 years ago
  7. 1b3207e CTDP: Only do TDP down/nominal change from TNP0 by Duncan Laurie · 12 years ago
  8. 55864ef ACPI: Add support for runtime config TDP down by Duncan Laurie · 12 years ago
  9. f4d3623 ELOG: Add support for a monotonic boot counter in CMOS by Duncan Laurie · 12 years ago
  10. 696262b More descriptive error messages in Sandybridge raminit code by Stefan Reinauer · 12 years ago
  11. 9c4c6ab ELOG: Fix boot count increment for non-wake case by Duncan Laurie · 12 years ago
  12. fe7b5d2 Ivybridge: fix workaround and enable PAIR by Duncan Laurie · 12 years ago
  13. 77dbbac CPU: Add basic support for Nominal Configurable TDP by Duncan Laurie · 12 years ago
  14. b91a0f2 Rename cache_lbmem() to cache_ramstage() by Stefan Reinauer · 12 years ago
  15. 6097e19 Make ACPI code detect Sandy/Ivy Bridge dynamically by Stefan Reinauer · 12 years ago
  16. afcaac2 Drop (empty) sandybridge_late_initialization() by Stefan Reinauer · 12 years ago
  17. baae2d2 Add support for HM70 and NM70 LPC bridge by Stefan Reinauer · 12 years ago
  18. 542e962 Print PCI ID of PCH during boot up by Stefan Reinauer · 12 years ago
  19. c664387 Drop leading spaces from CPU name string by Stefan Reinauer · 12 years ago
  20. 4821489 Fix MRC cache update delays by Stefan Reinauer · 12 years ago
  21. 496f4a0 SandyBridge: Add another PCI device ID for northbridge by Walter Murphy · 12 years ago
  22. da83a5f Fixes to enable RC6 on IvyBridge by Duncan Laurie · 12 years ago
  23. ce6e9fe i945: Disable IGD if plugin VGA is preferred by Patrick Georgi · 12 years ago
  24. 8bacc40 Fix udelay() implementation for i945 romstage by Nico Huber · 12 years ago
  25. cda9f93 Intel SCH northbridge: fix resource index by Kyösti Mälkki · 12 years ago
  26. cc55b9b Define global uma_memory variables by Kyösti Mälkki · 12 years ago
  27. d422069 i5000: Fix resource allocation by Sven Schnelle · 12 years ago
  28. 34d86f0 i5000: reset system if raminit fails by Sven Schnelle · 12 years ago
  29. 7b48379 i5000: Add PCI ids for all i5000 flavours by Sven Schnelle · 12 years ago
  30. 6444bd4 i945: Reset IGD on boot by Patrick Georgi · 12 years ago
  31. 1454685 i5000: fix another typo by Sven Schnelle · 12 years ago
  32. 39b47d2 i5000: fix typos by Sven Schnelle · 12 years ago
  33. 1a7a7e6 i5000: enforce hard reset by Sven Schnelle · 12 years ago
  34. 88fc0b9 Sandybridge: Remove remnants of FDT support from MRC cache code by Stefan Reinauer · 12 years ago
  35. 6e901fd Sandybridge: Fix MRC cache calculation by Stefan Reinauer · 12 years ago
  36. bb11e60 Hook up MRC cache update by Stefan Reinauer · 12 years ago
  37. 1244f4b Rework Sandybridge MRC cache handling by Stefan Reinauer · 12 years ago
  38. e166782 Clean up #ifs by Patrick Georgi · 12 years ago
  39. f125d80 Add missing newline to printk in Sandybridge init code by Stefan Reinauer · 12 years ago
  40. adc05c1 Make Intel i5000 specific options only appear on i5000 systems by Stefan Reinauer · 12 years ago
  41. cafedcf Strip quotes from Sandybridge MRC blob by Stefan Reinauer · 12 years ago
  42. 7a3f36a Sandybridge: Display platform information early by Vadim Bendebury · 12 years ago
  43. 8508cff Update Ivybridge GT power meter tables by Duncan Laurie · 12 years ago
  44. dd585b8 Update ivybridge graphics initialization by Duncan Laurie · 12 years ago
  45. 7b508dd Only send ME Dram Init Done message on Sandybridge by Duncan Laurie · 12 years ago
  46. 0ff99b7 Modify DMI init for IvyBridge by Vincent Palatin · 12 years ago
  47. e6063fe Fix Sandybridge/Ivybridge mainboards according to code review by Stefan Reinauer · 12 years ago
  48. 6ea86b1 Sandybridge: Temporarily disable MRC cache finding code by Stefan Reinauer · 12 years ago
  49. e9dfdd9 Reverse Vendor ID & Device ID for map_oprom_vendev() by Martin Roth · 12 years ago
  50. 16401b8 SMM: Add udelay on Sandybridge systems by Stefan Reinauer · 12 years ago
  51. 93b4ed9 Intel e7505: build as separate object file by Kyösti Mälkki · 12 years ago
  52. 97c064f Intel e7505: enable ECC scrubbing by Kyösti Mälkki · 12 years ago
  53. 77e4f7d Intel e7505: refactor only by Kyösti Mälkki · 12 years ago
  54. 26c7b86 Intel e7505: handlers for undocumented registers by Kyösti Mälkki · 12 years ago
  55. 2c2e78d Unify IO APIC address specification by Patrick Georgi · 13 years ago
  56. 5c1ff92 Intel e7505: cleanups by Kyösti Mälkki · 12 years ago
  57. 5bd271b Intel e7505: renames only by Kyösti Mälkki · 12 years ago
  58. 00636b0 Add support for Intel Sandybridge CPU (northbridge part) by Stefan Reinauer · 12 years ago
  59. eb5e28f Intel northbridge I945: Apply un-written naming rules by Kyösti Mälkki · 12 years ago
  60. c5fc7db Move C labels to start-of-line by Patrick Georgi · 12 years ago
  61. 334328a Avoid ../../.. paths in ASL files by Patrick Georgi · 13 years ago
  62. fdcd135 Rename i945 ACPI files to not carry an i945_ prefix by Patrick Georgi · 13 years ago
  63. bdc8c83 Remove non-existent include by Sven Schnelle · 13 years ago
  64. 332a7e9 i5000: halt second BSP by Sven Schnelle · 13 years ago
  65. 1767086 Add Intel i5000 Memory Controller Hub by Sven Schnelle · 13 years ago
  66. 751508a northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option by Peter Stuge · 13 years ago
  67. 784ffb3 i945: fix tsc udelay() by Sven Schnelle · 13 years ago
  68. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 13 years ago
  69. 0a0d5e8 Add support for E7505 northbridge. by Kyösti Mälkki · 13 years ago
  70. 481814d Clear improper use of CONFIG_CACHE_AS_RAM by Kyösti Mälkki · 13 years ago
  71. b15975b copy e7501 component to e7505 by Stefan Reinauer · 13 years ago
  72. 5563959 I945: replace #if defined() by #if by Sven Schnelle · 13 years ago
  73. ab87254 use acpi.h include instead of manually adding acpi_slp_type. by Stefan Reinauer · 13 years ago
  74. b9d60c9 fix compilation of intel/sch northbridge code with gcc 4.6 by Stefan Reinauer · 13 years ago
  75. 03169d3 Replace while with do; while to avoid repetition by Noe Rubinstein · 13 years ago
  76. 7981b94 Report GSE chipset and warn if the code has been compiled for the wrong chipset. by Stefan Reinauer · 13 years ago
  77. e089a3f northbridge/intel/i440bx: Registered SDRAM modules support and fixes by Keith Hui · 13 years ago
  78. b629d14 i945 GMA: restore tft brightness from cmos by Sven Schnelle · 13 years ago
  79. d8c68a9 i82801gx: replace cafed00d/cafebabe by defines by Sven Schnelle · 13 years ago
  80. b251753 Change read_option() to a macro that wraps some API uglyness by Patrick Georgi · 13 years ago
  81. 1d888a9 some ifdef --> if fixes by Stefan Reinauer · 13 years ago
  82. 148a4f5 i945: improve get_top_of_ram() by Sven Schnelle · 13 years ago
  83. 541269b [i945] Add SPD adress mapping by Sven Schnelle · 14 years ago
  84. 4096fc5 SMM code on i945 platforms needs udelay() by Peter Stuge · 14 years ago
  85. cdcf983 fix i810 boards with ram init debugging disabled. by Stefan Reinauer · 14 years ago
  86. fc01e5e proper printk handling in src/northbridge/intel/i82810/raminit.c by Stefan Reinauer · 14 years ago
  87. 1c2c750 dump_spd_registers() is only defined when ram init debugging is on. by Stefan Reinauer · 14 years ago
  88. 3c0bfaf Fix most CONFIG_DEBUG_RAM_SETUP issues. by Stefan Reinauer · 14 years ago
  89. 09f5a74 Fix build with CONFIG_DEBUG_RAM_SETUP on Intel 440BX, use printk(). by Keith Hui · 14 years ago
  90. bccbbe6 The same mechanisms are used for normal and fallback images. by Stefan Reinauer · 14 years ago
  91. 405721d Fix a few whitespace and coding style issues. by Uwe Hermann · 14 years ago
  92. a0360af A couple of Poulsbo fixes: by Patrick Georgi · 14 years ago
  93. be61a17 Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board which uses it. by Patrick Georgi · 14 years ago
  94. 259a39f fix according to coding guidelines by Stefan Reinauer · 14 years ago
  95. c436953 Following patch adds support for suspend/resume functions. I had to change the get_cbmem_toc because macro magic did not work well. by Rudolf Marek · 14 years ago
  96. 97be27e We hardcode highmemory size in every northbridge! This is bad, and especially if suspend to ram is involved. Let the default be taken from cbmem.h which also handles the suspend logic. by Rudolf Marek · 14 years ago
  97. 2b9070a catch some illegal configurations (trivial) by Stefan Reinauer · 14 years ago
  98. 8301d83 second round name simplification. drop the <component>_ prefix. by stepan · 14 years ago
  99. 4028ce7 Get rid of some unneeded function prototypes in romstage.c files. by Uwe Hermann · 14 years ago
  100. e87c38e After finding the missing bit poweroff works now. by Tobias Diedrich · 14 years ago