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review.coreboot.org / coreboot / 26e441f5bc381ec0fc476e4f78b4925a400c558c
  1. 26e441f x86emu: fix comment for BTS instruction by Stefan Reinauer · 12 years ago
  2. 911f446 x86emu: Add an RDTSC implementation to the x86 emulator by Stefan Reinauer · 12 years ago
  3. 08ef498 Intel 82810 and 82830: always room for PCI memory by Kyösti Mälkki · 12 years ago
  4. b5f5652 Intel i945 and sch: no memory over 4GB by Kyösti Mälkki · 12 years ago
  5. ecf1ed4 Allocators for different memory regions types by Kyösti Mälkki · 12 years ago
  6. 19e99f5 libpayload: Fix typo by Patrick Georgi · 12 years ago
  7. 48fcb53 x86emu: Use NULL instead of 0 when assigning pointer by Stefan Reinauer · 12 years ago
  8. d51f974 Re-run the git-describe if it fails at first try. by zbao · 12 years ago
  9. 188e3c2 Drop mainboard chip.h by Stefan Reinauer · 12 years ago
  10. efff733 Refactor driver structs by Patrick Georgi · 12 years ago
  11. 8730bf8 bd82x6x: Use CMOS variable if available for power-on on power failure by Stefan Reinauer · 12 years ago
  12. 7dc2864 amd/lx: Move configuration from source to Kconfig by Patrick Georgi · 12 years ago
  13. 1b3207e CTDP: Only do TDP down/nominal change from TNP0 by Duncan Laurie · 12 years ago
  14. 8de8844 ELOG: Fix reporting of developer/recovery modes by Duncan Laurie · 12 years ago
  15. c1c9435 Log event for abnormal management engine status by Duncan Laurie · 12 years ago
  16. 55864ef ACPI: Add support for runtime config TDP down by Duncan Laurie · 12 years ago
  17. 5563211 CPU: Add option to set TCC activation offset by Duncan Laurie · 12 years ago
  18. d6aca0b ACPI: Add a method to notify OS to re-read _PPC by Duncan Laurie · 12 years ago
  19. 0eefa00 ACPI: Add function to write _PPC using NVS by Duncan Laurie · 12 years ago
  20. 10d31ab NVS: Add a temp sensor ID and an ACPI Method to set it by Duncan Laurie · 12 years ago
  21. 708f731 ME: Move ME v8 lockdown to finalize step by Duncan Laurie · 12 years ago
  22. a0bec17 Reserve bd82x6x LPC decode ranges in the resource allocator by Marc Jones · 12 years ago
  23. 1bb79bc ELOG: Log run-time SMI southbridge events by Duncan Laurie · 12 years ago
  24. cfb64bd SATA: Add option to configure gen3 transmitter by Duncan Laurie · 12 years ago
  25. 0920915 ELOG: Support GSMI in CPT/PPT southbridge SMI handler by Duncan Laurie · 12 years ago
  26. 38bd80d Add correct bios callout into read event routine by zbao · 12 years ago
  27. 035f1d2 ibase/mb899: Rename NIC BIOS disable driver and hook up by Patrick Georgi · 12 years ago
  28. fce22e8 Remove copies of rtl8168.c by Patrick Georgi · 12 years ago
  29. 82704c6 USBDEBUG: buffer up to 8 bytes by Sven Schnelle · 12 years ago
  30. 0b7b7b6 Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs by Stefan Reinauer · 12 years ago
  31. c65a36e Enable Microcode in CBFS for all SandyBridge/IvyBridge systems by Stefan Reinauer · 12 years ago
  32. 79bbbd9 ELOG: Add support for SMM and kernel GSMI driver by Duncan Laurie · 12 years ago
  33. 62f1ad9 SMM: Fix state table for Intel Core2 CPUs by Stefan Reinauer · 12 years ago
  34. 54cba3b SMM: Skip locking SPI registers in finalize step by Duncan Laurie · 12 years ago
  35. 800e950 ELOG: Log boot-time events found in southbridge by Duncan Laurie · 12 years ago
  36. 27e5aac ELOG: Log events for Chrome OS developer/recovery mode by Duncan Laurie · 12 years ago
  37. c0f2cfb Fix comment to reference IvyBridge, too by Stefan Reinauer · 12 years ago
  38. 6d29c73 Include SandyBridge Microcode when IvyBridge is enabled by Stefan Reinauer · 12 years ago
  39. dcc17ae AMD parmer: Set correct azalia code verb table by zbao · 12 years ago
  40. 3726670 AMD family15tn: Add BIOS callback hook for getting VBIOS Image by zbao · 12 years ago
  41. a36d8b3 AMD Family 15tn: Set the default return value as AGESA_SUCCESS instead of TRUE by zbao · 12 years ago
  42. 19a1854 AMD Family15tn: Set the mask of MTRR to 0000FFFXX0000800 by zbao · 12 years ago
  43. 405cfe2 Change multiply ONE_MB to bit shifting. by zbao · 12 years ago
  44. ace7a6a SMM: rename tseg_fixup to tseg_relocate and export by Duncan Laurie · 12 years ago
  45. 0aa5b09 Fix date output in Microcode update by Stefan Reinauer · 12 years ago
  46. e6f459c CougarPoint/PantherPoint: Add HM77 device ID to table by Kimarie Hoot · 12 years ago
  47. ac3aa09 Extend smbios api to allow runtime change of mainboard serial and version by Christian Gmeiner · 12 years ago
  48. 594473d Remove useless semicolon by Patrick Georgi · 12 years ago
  49. be1ef23 chromeos: Pass pointer to ChromeOS ACPI structure instead of VB Shared Data by Stefan Reinauer · 12 years ago
  50. d59d624 sync the northbridge.c with other family. by zbao · 12 years ago
  51. 8d32b89 Fix LAPIC timer on Ivy Bridge systems by Stefan Reinauer · 12 years ago
  52. f4d3623 ELOG: Add support for a monotonic boot counter in CMOS by Duncan Laurie · 12 years ago
  53. 472ec9c ELOG: Add support for generating SMBIOS type15 table by Duncan Laurie · 12 years ago
  54. 696262b More descriptive error messages in Sandybridge raminit code by Stefan Reinauer · 12 years ago
  55. 0c32c97 bd82x6x: Drop unneeded pci_dev_t by Stefan Reinauer · 12 years ago
  56. 9c4c6ab ELOG: Fix boot count increment for non-wake case by Duncan Laurie · 12 years ago
  57. fe7b5d2 Ivybridge: fix workaround and enable PAIR by Duncan Laurie · 12 years ago
  58. 22935e1 CPU: Set flex ratio to nominal TDP ratio in bootblock by Duncan Laurie · 12 years ago
  59. 51cb26d SMM: Fix state save map for sandybridge and TSEG by Duncan Laurie · 12 years ago
  60. 181bbdd SMM: Add option for SPI driver to be available in SMM by Duncan Laurie · 12 years ago
  61. f5e9ac4 SMM: Add support for malloc in SMM if using TSEG by Duncan Laurie · 12 years ago
  62. 7d2b81c ELOG: Add support for flash based event log by Duncan Laurie · 12 years ago
  63. d2e00b9 SMM: Add heap region and move C handler higher in region by Duncan Laurie · 12 years ago
  64. 4e4320f CPU: Update ivybridge PP1 current limit value by Duncan Laurie · 12 years ago
  65. 77dbbac CPU: Add basic support for Nominal Configurable TDP by Duncan Laurie · 12 years ago
  66. b91a0f2 Rename cache_lbmem() to cache_ramstage() by Stefan Reinauer · 12 years ago
  67. 9764d4c Implement stack overflow checking for the BSP by Ronald G. Minnich · 12 years ago
  68. 9842ad8 Fix automatic ME detection in finalize by Stefan Reinauer · 12 years ago
  69. a306ad7 ChromeOS: Remove board specific acpi_get_vdat_info() by Stefan Reinauer · 12 years ago
  70. 998f3a2 Cougar/Panther Point: Compile in ME7 and ME8 code at the same time by Stefan Reinauer · 12 years ago
  71. 49058c0 Fix ME hash functions on Panther Point/Cougar Point by Stefan Reinauer · 12 years ago
  72. 999e94c Config changes to support microcode in CBFS by Vadim Bendebury · 12 years ago
  73. 48c6bae Add BAR address debug information to Oxford PCIe serial driver by Marc Jones · 12 years ago
  74. 39fea6e Add microcode blob processing by Vadim Bendebury · 12 years ago
  75. 537b4e0 Add code to read Intel microcode from CBFS by Vadim Bendebury · 12 years ago
  76. ef6b08c Add PCIe port disable debug message by Marc Jones · 12 years ago
  77. d81744e Make MAX_PHYSICAL_CPUS invisible on non-AMD boards by Stefan Reinauer · 12 years ago
  78. 9d3e832 bd82x6x: Support power-on-after-power-fail better by Stefan Reinauer · 12 years ago
  79. df0c822 Rename microcode include file to be model agnostic by Vadim Bendebury · 12 years ago
  80. 8bdbddf Fix function generating GPIO state based vector by Vadim Bendebury · 12 years ago
  81. 6097e19 Make ACPI code detect Sandy/Ivy Bridge dynamically by Stefan Reinauer · 12 years ago
  82. 3a8cad3 Shrink the stack sizes we need in coreboot by Ronald G. Minnich · 12 years ago
  83. 3f6a4d7 Add specific power management init code for PantherPoint by Duncan Laurie · 12 years ago
  84. afcaac2 Drop (empty) sandybridge_late_initialization() by Stefan Reinauer · 12 years ago
  85. b405857 Remove CMOS Extended range enable from romstage by Duncan Laurie · 12 years ago
  86. 8e515d3 RTC: Enable extended CMOS in the bootblock by Duncan Laurie · 12 years ago
  87. 9a380ab bd82x6x: Convert all PCI ID lists to new scheme by Stefan Reinauer · 12 years ago
  88. baae2d2 Add support for HM70 and NM70 LPC bridge by Stefan Reinauer · 12 years ago
  89. b5dfcae cs5536: add smbus support in ramstage by Christian Gmeiner · 12 years ago
  90. fa418e3 Add uartmem_init prototype. by Marc Jones · 12 years ago
  91. c8c836f RTC: Add defines for standard clock offsets by Duncan Laurie · 12 years ago
  92. 542e962 Print PCI ID of PCH during boot up by Stefan Reinauer · 12 years ago
  93. a9f670a ifdtool: Use perror for file write errors by Stefan Reinauer · 12 years ago
  94. c664387 Drop leading spaces from CPU name string by Stefan Reinauer · 12 years ago
  95. b38e0c3 Properly identify ACPI C3 states in _CST table. by Duncan Laurie · 12 years ago
  96. 52e6118 Remove unused free() function by Stefan Reinauer · 12 years ago
  97. fe5539c Add standard header to prevent multiple inclusion by Vadim Bendebury · 12 years ago
  98. 2198c58 Move GGL0001 ACPI code to generic ChromeOS code by Stefan Reinauer · 12 years ago
  99. 4821489 Fix MRC cache update delays by Stefan Reinauer · 12 years ago
  100. 305b19d Remove code that enables/disables VMX in coreboot on chromebooks. by Ronald G. Minnich · 12 years ago