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review.coreboot.org / coreboot / 25c7d9342b8bdee61710a516440e4b9c4b83fb09 / src / soc / intel / skylake / chip_fsp20.c
  1. 25c7d93 soc/intel/skylake: Disable s0ix if not enabled in devicetree by Duncan Laurie · 7 years ago
  2. a4b11e5c soc/intel/skylake: Perform CPU MP Init before FSP-S Init by Subrata Banik · 8 years ago
  3. 7a0044b Revert: soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1 by Duncan Laurie · 8 years ago
  4. 32997fb soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1 by Barnali Sarkar · 8 years ago
  5. 7d48410 skylake: Do not pass VBT to FSP if display init not required by Duncan Laurie · 8 years ago
  6. 6c191d8 romstage_handoff: add helper to determine resume status by Aaron Durbin · 8 years ago
  7. 6467014 soc/intel/skylake: Use SendVrMbxCmd1 for FSP 2.0 by Rizwan Qureshi · 8 years ago
  8. eedf6d8 soc/intel/skylake: Disable Legacy PME for Root ports by Naresh G Solanki · 8 years ago
  9. 2c3054c soc/intel/skylake: Add USB Port Over Current (OC) Pin programming by Subrata Banik · 8 years ago
  10. c6ec8dd fsp2_0: implement stage cache for silicon init by Brandon Breitenstein · 8 years ago
  11. ed14a4e soc/intel/skylake: move i2c voltage config to own variable by Aaron Durbin · 8 years ago
  12. a2d4062 soc/intel/skylake: Add FSP 2.0 support in ramstage by Naresh G Solanki · 8 years ago
  13. 1222a73 skylake: Add initial FSP2.0 support by Rizwan Qureshi · 8 years ago[Copied (61%) from src/soc/intel/skylake/include/soc/ramstage.h]
  14. 2f6fb9f skylake: Add ACPI device name handler by Duncan Laurie · 8 years ago
  15. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  16. 94b856e FSP 1.1: Move common FSP code by Lee Leahy · 9 years ago
  17. 1d14b3e soc/intel: Add Skylake SOC support by Lee Leahy · 9 years ago
  18. b000513 soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC by Lee Leahy · 9 years ago