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review.coreboot.org / coreboot / 1eecb8c814fa05e9902ddcb139a6e8b3a226ffa6 / src / mainboard / asrock / g41c-gs / variants / g41c-gs-r2 / devicetree.cb
  1. 1eecb8c nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree by Arthur Heymans · 1 year, 8 months ago
  2. 50863da src/mainboard to src/security: Fix spelling errors by Martin Roth · 2 years, 10 months ago
  3. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 2 months ago
  4. 674ad92 src/mainboard: Replace GPLv2 long form headers with SPDX header by Elyes HAOUAS · 4 years, 2 months ago
  5. 3b618bb mainboard/[a-f]*: Remove copyright notices by Patrick Georgi · 4 years, 4 months ago
  6. fecf777 sb/intel/i82801gx: Add common LPC decode code by Arthur Heymans · 4 years, 8 months ago
  7. 5eb81be sb/intel/i82801gx: Detect if the southbridge supports AHCI by Arthur Heymans · 6 years ago
  8. fbf380a mb/*/devicetree.cb: Remove unavailable PCIe ports by Arthur Heymans · 6 years ago
  9. b9d2589 mb/*/*: Harmonise FD and devicetree on boards featuring ICH7 by Arthur Heymans · 6 years ago
  10. 33fa95c mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree by Arthur Heymans · 6 years ago
  11. e98f305 mb/asrock/g41c-gs: Add the revision 1 variant by Arthur Heymans · 7 years ago[Renamed from src/mainboard/asrock/g41c-gs/devicetree.cb]
  12. fd440bb mb/asrock/g41c-gs: Fix the SATA clock output on ck505 by Arthur Heymans · 7 years ago
  13. 7d46e96 mainboard: Add ASRock G41C-GS by Arthur Heymans · 7 years ago