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review.coreboot.org / coreboot / 1e24bf3f719f82c16fd577e87900e1aa0fd6605b / src / soc / intel / fsp_broadwell_de
  1. e8c527e intel: Fix copy/paste error in license text by Marshall Dawson · 7 years ago
  2. 4fb64d0 fsp 1.0 systems: Check for NULL when saving HobListPtr by Martin Roth · 7 years ago
  3. c2973d1 spi: Get rid of SPI_ATOMIC_SEQUENCING by Furquan Shaikh · 8 years ago
  4. 3d15e10 MMCONF_SUPPORT: Flip default to enabled by Kyösti Mälkki · 8 years ago
  5. 94f8699 spi: Define and use spi_ctrlr structure by Furquan Shaikh · 8 years ago
  6. 36b81af spi: Pass pointer to spi_slave structure in spi_setup_slave by Furquan Shaikh · 8 years ago
  7. 0dba025 spi: Fix parameter types for spi functions by Furquan Shaikh · 8 years ago
  8. afe8aee lib: put romstage_handoff implementation in own compilation unit by Aaron Durbin · 8 years ago
  9. bac0fad Remove explicit select MMCONF_SUPPORT by Kyösti Mälkki · 8 years ago
  10. 913684c soc/intel/fsp_broadwell_de: Fix system hang when timestamp is enabled by York Yang · 8 years ago
  11. ab5f3d1 soc/intel/fsp_broadwell_de: Remove the enforced fsp1.0 APIs call sequence by York Yang · 8 years ago
  12. bc97b4e soc/intel/fsp_broadwell_de/uart: Drop it by Nico Huber · 8 years ago
  13. 4f2754c fsp_broadwell_de: Add Kconfig switch for SERIRQ operation mode by Werner Zeh · 8 years ago
  14. 9d18e33 siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPC by Werner Zeh · 8 years ago
  15. 91aea42 fsp_broadwell_de: Correct access to SIRQ_CNTL register by Werner Zeh · 8 years ago
  16. b5026bf fsp_broadwell_de: Adjust printed address in SPI debug messages by Werner Zeh · 8 years ago
  17. 62d1313 fsp_broadwell_de: Refactor code for SPI debug messages by Werner Zeh · 8 years ago
  18. d7127b0 fsp_Broadwell_DE: Do not set IRQ3 and IRQ4 to level by Kevin Paul Herbert · 8 years ago
  19. 1cfb555 fsp_broadwell_de: Add DMAR table to ACPI by Werner Zeh · 8 years ago
  20. 0cd338e Remove non-ascii & unprintable characters by Martin Roth · 8 years ago
  21. bb9722b Add newlines at the end of all coreboot files by Martin Roth · 8 years ago
  22. 038e724 src/soc: Capitalize CPU, ACPI, RAM and ROM by Elyes HAOUAS · 8 years ago
  23. c159bb0 soc/intel/fsp_broadwell_de: use common Intel ACPI hardware definitions by Aaron Durbin · 8 years ago
  24. 7804790 fsp_broadwell_de: Add SMBus driver for ramstage by Werner Zeh · 8 years ago
  25. 93db5a5 intel/fsp_broadwell_de: Do not use hard coded SCI IRQ for ACPI by Werner Zeh · 8 years ago
  26. 9007ffd PCI: Use PCI_DEVFN macro instead of DEV_FUNC by Werner Zeh · 8 years ago
  27. 61f4b42 fsp_broadwell_de: Enable Super I/O address range decode by Werner Zeh · 8 years ago
  28. 65e8f64 intel romstage: Use run_ramstage() by Kyösti Mälkki · 8 years ago
  29. 8346b04 soc/intel/fsp_broadwell_de: convert to using common MP init by Aaron Durbin · 8 years ago
  30. 0e55632 cpu/x86/mp_init: remove unused callback arguments by Aaron Durbin · 8 years ago
  31. cccef341 intel/fsp_broadwell_de: fix SPD CBFS file type by Stef van Os · 8 years ago
  32. bfe5726 broadwell_de_fsp: Select HAVE_INTEL_FIRMWARE by Werner Zeh · 8 years ago
  33. d7cba28 soc/intel: Add Broadwell-DE SoC support by York Yang · 8 years ago