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review.coreboot.org / coreboot / 1a5ce95815210032783d01e830390ee5b6a54dc5 / src / mainboard / siemens / mc_apl1 / variants / mc_apl5 / mainboard.c
  1. 1a5ce95 siemens/mc_apl5: Disable PCI clock outputs on XIO bridges by Mario Scheithauer · 6 years ago
  2. a94a153 siemens/mc_apl5: Set bus master bit for on-board PCI device by Mario Scheithauer · 6 years ago
  3. 5716b4c siemens/mc_apl5: Add new mainboard variant mc_apl5 by Mario Scheithauer · 6 years ago