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coreboot
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1a5ce95815210032783d01e830390ee5b6a54dc5
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src
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mainboard
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siemens
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mc_apl1
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variants
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mc_apl5
/
mainboard.c
1a5ce95
siemens/mc_apl5: Disable PCI clock outputs on XIO bridges
by Mario Scheithauer
· 6 years ago
a94a153
siemens/mc_apl5: Set bus master bit for on-board PCI device
by Mario Scheithauer
· 6 years ago
5716b4c
siemens/mc_apl5: Add new mainboard variant mc_apl5
by Mario Scheithauer
· 6 years ago