Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 17ad4598e9d3d302cc45c86a8e11aac62928c83c / src / northbridge / intel
  1. 17ad459 nb/intel/*: Account for cbmem_top alignment by Arthur Heymans · 6 years ago
  2. 794f56b nb/intel/i945: Fix domain resources by Arthur Heymans · 6 years ago
  3. a342f39 src: Remove unneeded whitespace by Elyes HAOUAS · 6 years ago
  4. 45022ae intel: Use CF9 reset (part 1) by Patrick Rudolph · 6 years ago
  5. 4fe0cba nb/intel/nehalem: Remove unneeded whitespace by Elyes HAOUAS · 6 years ago
  6. b1ba662 nb/intel/x4x: Fix P45 CAPID max frequency by Arthur Heymans · 6 years ago
  7. 8ddd7d1 nb/intel/x4x: Program read training results to all ranks by Arthur Heymans · 6 years ago
  8. 419bfbc src: Move common IA-32 MSRs to <cpu/x86/msr.h> by Elyes HAOUAS · 6 years ago
  9. 603963e src: Replace MSR addresses with macros by Elyes HAOUAS · 6 years ago
  10. d44221f Move compiler.h to commonlib by Nico Huber · 6 years ago
  11. 88607a4 src: Use tabs for indentation by Elyes HAOUAS · 6 years ago
  12. ef20ecc nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address by Elyes HAOUAS · 6 years ago
  13. 5b2a2d0 src/*: normalize Google copyright headers by Patrick Georgi · 6 years ago
  14. b60920d northbridge: Use 'unsigned int' to bare use of 'unsigned' by Elyes HAOUAS · 6 years ago
  15. b0c6cff nb/intel/x4x: Don't use cached settings if CPU FSB has been changed by Arthur Heymans · 6 years ago
  16. 9ce5974 nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resume by Nico Huber · 6 years ago
  17. 75a62e7 complier.h: add __always_inline and use it in code base by Aaron Durbin · 6 years ago
  18. 3e3bae0 nb/intel/x4x/gma.c: fix skipping of native graphics init by Stefan Tauner · 6 years ago
  19. e6c8f7e nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled by Arthur Heymans · 6 years ago
  20. 24efe73 nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.c by Patrick Rudolph · 6 years ago
  21. eb6f2f5 nb/intel/pineview: Use a common MMCONF_BASE_ADDRESS by Arthur Heymans · 6 years ago
  22. 015339f nb/intel/pineview: Use the correct address for the RCVEN strobe by Arthur Heymans · 6 years ago
  23. 1f6369e nb/intel/pineview: Use i2c block read to fetch SPD by Arthur Heymans · 6 years ago
  24. 2de750b nb/intel/raminit: Remove unused headers by Patrick Rudolph · 6 years ago
  25. 08c9a7c nb/intel/sandybridge/raminit: Fix DIMM type mapping by Patrick Rudolph · 6 years ago
  26. 15e6469 nb/intel/sandybridge: Fill in DIMM serial number by Patrick Rudolph · 6 years ago
  27. 89af71c sandybridge/raminit_common.c: fix printram statement by Iru Cai · 6 years ago
  28. 1faa11e Fix PCI ACPI _OSC methods by Marc Jones · 6 years ago
  29. 8da2fa0 nb/intel/haswell: Always locate mrc.bin in the COREBOOT fmap region by Arthur Heymans · 6 years ago
  30. 3d45000 src: Fix typo by Elyes HAOUAS · 6 years ago
  31. 64f6b71 src/northbridge: Fix typo by Elyes HAOUAS · 6 years ago
  32. 3a2f900 x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2] by Felix Held · 6 years ago
  33. f83d80b nehalem/raminit: remove read_mchbar functions by Felix Held · 6 years ago
  34. 22ca8cb nehalem/raminit: clean up code and remove write_mchbar functions by Felix Held · 6 years ago
  35. 752cdbc northbridge/nehalem: add MCHBAR8/16 AND_OR macros by Felix Held · 6 years ago
  36. 04be2dd nehalem/raminit: clean up code and use MCHBAR macros by Felix Held · 6 years ago
  37. 29a9c07 nehalem/raminit: remove REAL define and most dead code by Felix Held · 6 years ago
  38. ad691ad sandybridge/raminit_mrc: remove reference to report_platform_info() by Matt DeVillier · 6 years ago
  39. 9fe248f sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining places by Felix Held · 6 years ago
  40. 9cf1dd2 sandybridge/raminit_common: use macro for execute command queue register by Felix Held · 6 years ago
  41. f9b826a sandybridge/raminit_common: use FOR_ALL_CHANNELS macro by Felix Held · 6 years ago
  42. b802c07 sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [2/2] by Felix Held · 6 years ago
  43. 2463aa9 sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [1/2] by Felix Held · 6 years ago
  44. fe68a77 northbridge/sandybridge: add MCHBAR32 AND/OR/AND_OR access macros by Felix Held · 6 years ago
  45. 8908931 nb/intel/gm45: Don't use PCI operations on the pci_domain device by Arthur Heymans · 6 years ago
  46. 15e1b39 nb/intel/pineview: Don't use PCI operations on the pci_domain device by Arthur Heymans · 6 years ago
  47. c6e13b6 nb/intel/x4x: Don't use PCI operations on the pci_domain device by Arthur Heymans · 6 years ago
  48. 1704120 nb/intel/sandybridge: Don't use PCI operations on the pci_domain device by Arthur Heymans · 6 years ago
  49. 432575c x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2] by Felix Held · 6 years ago
  50. aade90e nb/intel/gm45: Use common code for SMM in TSEG by Arthur Heymans · 7 years ago
  51. 6cd2c2f northbridge/x4x: add MCHBAR AND/OR/AND_OR access macros by Felix Held · 6 years ago
  52. 86b299a northbridge/nehalem: add MCHBAR AND/OR/AND_OR macros by Felix Held · 6 years ago
  53. 00d2b91 northbridge/nehalem: clean up header file by Felix Held · 6 years ago
  54. 2bb3cdf sandybridge/raminit_common: use MCHBAR32 macro everywhere by Felix Held · 6 years ago
  55. 55823c3 sandybridge/raminit: use MCHBAR32 macro everywhere by Felix Held · 6 years ago
  56. b9267f0 sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macros by Felix Held · 6 years ago
  57. 708cf4b nb/intel/sandybridge: Bump MRC_CACHE_VERSION by Patrick Rudolph · 6 years ago
  58. ef8c559 nb/intel/sandybridge/report_platform: Move remaining code to sb folder by Patrick Rudolph · 6 years ago
  59. 9e1b9b5 nb/intel/sandybridge: Move CPU report to cpu folder by Patrick Rudolph · 6 years ago
  60. 74203de intel/sandybridge: Don't hardcode platform type by Patrick Rudolph · 7 years ago
  61. 5af2dea nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus width by Patrick Rudolph · 7 years ago
  62. 652c491 nb/intel/sandybridge/raminit: Fix PDWN_mode on desktops by Patrick Rudolph · 7 years ago
  63. 4c2f26c nb/intel/nehalem: Remove the C native graphic init by Arthur Heymans · 6 years ago
  64. db70f3b drivers/tpm: Add TPM ramstage driver for devices without vboot. by Philipp Deppenwiese · 6 years ago
  65. b009ac4 nb/intel/sandybridge/raminit: Fix non ASCII char by Patrick Rudolph · 6 years ago
  66. 5ee9bc1 nb/intel/sandybridge/raminit: Set REFIx9 according to spec by Patrick Rudolph · 7 years ago
  67. a4fc7be nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMs by Elyes HAOUAS · 6 years ago
  68. fd051dc src/northbridge: Use "foo *bar" instead of "foo* bar" by Elyes HAOUAS · 6 years ago
  69. 21b71ce6 src/nb: Fix non-local header treated as local by Elyes HAOUAS · 6 years ago
  70. 7866d49 arch/x86/acpi: Add DMAR RMRR helper functions by Matt DeVillier · 6 years ago
  71. a8a9f34 sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables by Arthur Heymans · 7 years ago
  72. e798e6a sb/intel/i82801ix: Use the common ACPI pirq generator by Arthur Heymans · 7 years ago
  73. fe25107 nb/intel/i945: Remove dead code by Elyes HAOUAS · 6 years ago
  74. 58a8953 Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location" by Arthur Heymans · 6 years ago
  75. 371e7d9 nb/intel/e7505: Leave ROM as un-cacheable in postcar by Kyösti Mälkki · 6 years ago
  76. aea8eec nb/intel/i440bx: Switch to POSTCAR_STAGE by Kyösti Mälkki · 6 years ago
  77. 5469907 nb/intel/i440bx: Move to RELOCATABLE_RAMSTAGE by Kyösti Mälkki · 6 years ago
  78. 54d6a28 cpu/intel/slot_1: Switch to different CAR setup by Kyösti Mälkki · 6 years ago
  79. 847f12b nb/intel/nehalem: Fix DEVEN defines by Patrick Rudolph · 6 years ago
  80. df946b8 nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset by Arthur Heymans · 6 years ago
  81. faa5f98 cpu/intel/haswell: Use the common intel romstage_main function by Arthur Heymans · 6 years ago
  82. 5e2ac2c nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xce by Elyes HAOUAS · 7 years ago
  83. e809305 nb/intel/x4x: Deprecate native graphic init by Arthur Heymans · 6 years ago
  84. 7345a17 nb/intel/x4x: Fix a few things in set_enhanced_mode by Arthur Heymans · 6 years ago
  85. 5a9dbde nb/intel/x4x: Work around a quirk by Arthur Heymans · 6 years ago
  86. 0602ce6 nb/intel/x4x: Add the option for stacked channel map settings by Arthur Heymans · 6 years ago
  87. b0f1988 src: Get rid of unneeded whitespace by Elyes HAOUAS · 6 years ago
  88. f2dd049 libgfxinit: Enable G45 support (for GM45/X4X) by Nico Huber · 7 years ago
  89. 4bdfebd nb/intel/pineview: Enable and allocate 8M for TSEG by Arthur Heymans · 6 years ago
  90. e07df9d nb/intel/i945: Enable and allocate 8M for TSEG by Arthur Heymans · 6 years ago
  91. f6d1477 nb/intel/i945: Add a common function to compute TSEG size by Arthur Heymans · 7 years ago
  92. 58d6ff1 intel/e7505: Remove ROMCC workaround by Kyösti Mälkki · 6 years ago
  93. 730df3c arch/x86: Make RELOCATABLE_RAMSTAGE the default by Kyösti Mälkki · 8 years ago
  94. 7904e72 arch/x86: Flag platforms without RELOCATABLE_RAMSTAGE by Kyösti Mälkki · 6 years ago
  95. 88af0f3 cpu/intel/haswell: Switch to POSTCAR_STAGE by Arthur Heymans · 6 years ago
  96. 02b13fd cpu/intel/model_2065x: Switch to POSTCAR_STAGE by Arthur Heymans · 6 years ago
  97. 6fcd7b8 cpu/intel/model_206ax: Switch to POSTCAR_STAGE by Arthur Heymans · 6 years ago
  98. 3a4edb6 nb/intel/gm45: Switch to POSTCAR_STAGE by Arthur Heymans · 6 years ago
  99. 4ff675e nb/intel/x4x: Switch to POSTCAR_STAGE by Arthur Heymans · 6 years ago
  100. aa7cf55 nb/intel/pineview: Switch to POSTCAR_STAGE by Arthur Heymans · 6 years ago