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review.coreboot.org / coreboot / 128c104c4d3b91d3371b03840af460d776af819d / src / northbridge / intel / gm45 / raminit.c
  1. 128c104 nb/intel: Fix some spelling mistakes in comments and strings by Martin Roth · 8 years ago
  2. 10141c3 nb/intel/gm45: Use LAPIC udelay instead of custom version by Arthur Heymans · 8 years ago
  3. 266a1f7 nb/intel/raminit (native): Read PCI mmio size from devicetree by Patrick Rudolph · 8 years ago
  4. 5aaeb27 nb/intel/gm45: Export low-power and (SFF) options by Nico Huber · 9 years ago
  5. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  6. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  7. bde6d30 x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer by Kevin Paul Herbert · 10 years ago
  8. 56ae8a0 gm45: Decrease MTRR usage by Vladimir Serbinenko · 10 years ago
  9. 9907be4 gm45: Reserve RAM for ME if it's active. by Vladimir Serbinenko · 10 years ago
  10. c4d8948 gm45: Move spd address map to board-specific config. by Vladimir Serbinenko · 10 years ago
  11. 7116ac8 src: Make use of 'CEIL_DIV(a, b)' macro across tree by Edward O'Callaghan · 10 years ago
  12. 931c1dc stdlib: Drop duplicates of min() and max() by Kyösti Mälkki · 10 years ago
  13. 24d1d4b x86: Unify arch/io.h and arch/romcc_io.h by Stefan Reinauer · 11 years ago
  14. 2efc880 intel/gm45: new northbridge by Patrick Georgi · 12 years ago