Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 0ca2a0654ca4b403e8a54d558bce07a862820a9d / src / include / cpu / x86 / msr.h
  1. 0ca2a06 src/include: Fix unsigned warnings by Lee Leahy · 7 years ago
  2. 8ffd050 src/include: Improve code formatting by Elyes HAOUAS · 8 years ago
  3. 918535a src/include: Capitalize CPU, RAM and ROM by Elyes HAOUAS · 8 years ago
  4. ae738ac cpu/x86: Support CPUs without rdmsr/wrmsr instructions by Lee Leahy · 8 years ago
  5. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 13 years ago
  6. 78301d0 AMD Fam10 code breaks with gcc 4.5.0. by Scott Duplichan · 14 years ago
  7. f333ba0 This commit updates the Geode LX GLCP delay control setup from the v2 way to the v3 way. by Edwin Beasant · 14 years ago
  8. 14e2277 Since some people disapprove of white space cleanups mixed in regular commits by Stefan Reinauer · 14 years ago
  9. 35b6bbb drop unneeded __ROMCC__ checks when the check for __PRE_RAM__ is more by Stefan Reinauer · 14 years ago
  10. 1d6d45e Split the two usages of __ROMCC__: by Myles Watson · 15 years ago
  11. 6ca7636 Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51 by arch import user (historical) · 19 years ago
  12. c84c190 - Renamed cpu header files by Eric Biederman · 20 years ago