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review.coreboot.org / coreboot / 09f3b6cf21d735b115d25bf081240979dccd0afc / src / mainboard / google / brya / romstage.c
  1. 09f3b6c mb, soc: change mainboard_memory_init_params prototype by Zhuohao Lee · 2 years, 7 months ago
  2. 126162c mb/google/brya: Enable DDR4 SODIMM for brask by David Wu · 3 years, 1 month ago[Renamed (81%) from src/mainboard/google/brya/romstage_spd_cbfs.c]
  3. f55e82c mb/google/brya: Add support for romstage GPIO table by Tim Wawrzynczak · 3 years ago
  4. c0308eb mb/google/brya: Introduce new baseboard brask by Zhuohao Lee · 3 years, 1 month ago[Renamed from src/mainboard/google/brya/romstage.c]
  5. 0007fa9 soc/intel/alderlake: Update mainboard_memory_init_params() argument by Subrata Banik · 3 years, 2 months ago
  6. 71f69dd Revert "mb/google/brya/brya0: Manually probe fw_config for DB_LTE" by Tim Wawrzynczak · 3 years, 3 months ago
  7. 2f8a704 mb/google/brya/brya0: Manually probe fw_config for DB_LTE by Tim Wawrzynczak · 3 years, 3 months ago
  8. 56868b8 mb/google/brya: Add memory DQ map by Eric Lai · 3 years, 8 months ago
  9. 5088682 mb/google/brya: Add entry stubs of each stage by Eric Lai · 3 years, 9 months ago