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coreboot
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0650cd0bad2816886745c4a7ffe0e7a1aefb9957
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src
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southbridge
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intel
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bd82x6x
/
lpc.c
0650cd0
southbridge/bd82x6x: Reserve 16 MiB for flash and not 8.
by Vladimir Serbinenko
· 11 years ago
35c0f43
Move nehalem/sandy/ivy to per-device acpi
by Vladimir Serbinenko
· 10 years ago
264d265
southbridge: Trivial - drop trailing blank lines at EOF
by Edward O'Callaghan
· 10 years ago
c3ed886
intel boards: Use acpi_is_wakeup_s3()
by Kyösti Mälkki
· 10 years ago
9c50e6a
Intel BD82x6x: LPC: Unify I/O APIC setup
by Paul Menzel
· 11 years ago
8c937c7
Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2
by Vladimir Serbinenko
· 11 years ago
a46a712
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
by Paul Menzel
· 11 years ago
a0bec17
Reserve bd82x6x LPC decode ranges in the resource allocator
by Marc Jones
· 12 years ago
800e950
ELOG: Log boot-time events found in southbridge
by Duncan Laurie
· 12 years ago
e6f459c
CougarPoint/PantherPoint: Add HM77 device ID to table
by Kimarie Hoot
· 12 years ago
3f6a4d7
Add specific power management init code for PantherPoint
by Duncan Laurie
· 12 years ago
9a380ab
bd82x6x: Convert all PCI ID lists to new scheme
by Stefan Reinauer
· 12 years ago
baae2d2
Add support for HM70 and NM70 LPC bridge
by Stefan Reinauer
· 12 years ago
95be1d6
Don't disable ACPI in the S3 resume path
by Duncan Laurie
· 12 years ago
459b777
add new LPC controller device ID value
by Vadim Bendebury
· 12 years ago
8e07382
Add support for Intel Panther Point PCH
by Stefan Reinauer
· 12 years ago