Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
04c5bae39054aedbff1865d9dd2633260c23ece3
/
src
/
southbridge
/
intel
/
bd82x6x
/
finalize.c
04c5bae
Define post codes for OS boot and resume
by Duncan Laurie
· 12 years ago
312ee0c
SPI: re-init SMM SPI driver after lockdown
by Duncan Laurie
· 12 years ago
f1c76ef
ELOG: Don't disable SPI controller lockdown
by Duncan Laurie
· 12 years ago
54cba3b
SMM: Skip locking SPI registers in finalize step
by Duncan Laurie
· 12 years ago
8e07382
Add support for Intel Panther Point PCH
by Stefan Reinauer
· 12 years ago