Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 00636b0daefc3c499990744226a0e1a316d71731
  1. 00636b0 Add support for Intel Sandybridge CPU (northbridge part) by Stefan Reinauer · 12 years ago
  2. 4dd3853 Ignore .exe files in whitespace test by Patrick Georgi · 12 years ago
  3. 92cfe18 Add getopt implementation to abuild by Patrick Georgi · 12 years ago
  4. fb89dd0 Use fast memset in SMM mode, too by Stefan Reinauer · 12 years ago
  5. 8e07382 Add support for Intel Panther Point PCH by Stefan Reinauer · 12 years ago
  6. cb91e15 Add support for mainboard specific suspend/resume handler by Stefan Reinauer · 12 years ago
  7. ec20763 Move TPM code to romstage by Stefan Reinauer · 12 years ago
  8. 1551183 Drop verified boot code from acpi.c by Stefan Reinauer · 12 years ago
  9. f13772a Drop duplicate inclusion of src/vendorcode by Stefan Reinauer · 12 years ago
  10. 3aa067f Add support to run SMM handler in TSEG instead of ASEG by Stefan Reinauer · 12 years ago
  11. 6efbebd libpayload: avoid excessive casts in printf.c by Mathias Krause · 12 years ago
  12. 67997d3 libpayload: minor cleanups by Mathias Krause · 12 years ago
  13. f17789c Don't unconditionally show ChromeOS options by Stefan Reinauer · 12 years ago
  14. ea37a21 Add support for Intel Turbo Boost feature by Stefan Reinauer · 12 years ago
  15. 3d7c677 smbios: add support for onboard devices extended information by Stefan Reinauer · 12 years ago
  16. 4a2daf6 nvramtool: 64bit safe CBFS handling by Patrick Georgi · 12 years ago
  17. 3bbd2bf Add preprocessing capabilities to the cbfs-files mechanism by Patrick Georgi · 12 years ago
  18. 499fc92 Add nvramtool to coreboot build system by Patrick Georgi · 12 years ago
  19. abdf15f Apply cache-as-ram conditionally on socket mPGA604 by Kyösti Mälkki · 12 years ago
  20. afd141d S3 code whitespaces changes. by zbao · 12 years ago
  21. 01bd79f Add sb800 spi support. by zbao · 12 years ago
  22. 971804e x86, oprom: ensure DF is always cleared by Mathias Krause · 12 years ago
  23. 74a0efe [ChromeOS] Don't initialize VGA Option ROM in normal mode by Stefan Reinauer · 12 years ago
  24. 020b22a Add EC component for SMSC MEC1308/1310 by Stefan Reinauer · 12 years ago
  25. b0dd1d9 Add support for ITE IT8772F SuperI/O chip by Stefan Reinauer · 12 years ago
  26. dc8448fd Add a helper function to determine the number of enabled CPUs by Stefan Reinauer · 12 years ago
  27. d40393e Align: Make sure 1 is treated as unsigned long instead of int by Stefan Reinauer · 12 years ago
  28. 9aea04a Add Google ChromeOS vendor support by Stefan Reinauer · 12 years ago
  29. c302d20 Force coreboot mconf to create temp files in the output directory by Vadim Bendebury · 13 years ago
  30. e1bb49e Add a "remove" command to cbfstool by Gabe Black · 13 years ago
  31. dd30acd Fix issues with x86 memcpy by Mathias Krause · 12 years ago
  32. 819c7d4 Whitespace fixes by Patrick Georgi · 12 years ago
  33. 087b24d Update xcompile to search for x86_64 toolchain. by Marc Jones · 12 years ago
  34. b9fa1ed Make libpayload parse the coreboot tables before setting up the consoles by Gabe Black · 12 years ago
  35. cbb648c Enable -Werror for romcc by Stefan Reinauer · 12 years ago
  36. d086d51 Keep cscope.out when distclean. by zbao · 12 years ago
  37. a860c68 Intel cpus: get MAXPHYADDR at runtime for new CAR by Kyösti Mälkki · 12 years ago
  38. 0078ceb Intel cpus: add hyper-threading CPU support to new CAR by Kyösti Mälkki · 12 years ago
  39. 05d6ffb Intel cpus: improve CPU compatibility of new CAR by Kyösti Mälkki · 13 years ago
  40. 7dfe32c Add support for RAM-less multi-processor init by Kyösti Mälkki · 13 years ago
  41. f9d1a42 Intel cpus: apply some good programming practices in new CAR by Kyösti Mälkki · 12 years ago
  42. 325b92f Intel cpus: cache actual size of the Flash ROM device by Kyösti Mälkki · 12 years ago
  43. 5a660ca Intel cpus: copy model_6ex CAR code by Kyösti Mälkki · 12 years ago
  44. d842f1f Makefile: rename romstage linking filenames by Kyösti Mälkki · 12 years ago
  45. a01ec14 Makefile: split romstage linking to separate rules by Kyösti Mälkki · 12 years ago
  46. 608d15b Fix coreboot makefiles not to produce half baked output. by Kyösti Mälkki · 12 years ago
  47. 5fdc00a Drop obsolete TINY_BOOTBLOCK by Kyösti Mälkki · 12 years ago
  48. a7b296d Fix warnings in coreboot utilities. by Stefan Reinauer · 13 years ago
  49. 8acbc2a use movsl for copying resume memory back by Stefan Reinauer · 13 years ago
  50. 77adc5e Don't unconditionally add support for cardbus and pci-x devices by Stefan Reinauer · 13 years ago
  51. dfb098d Add DEBUG_TPM option to Debugging menu by Stefan Reinauer · 13 years ago
  52. 7b67892 Make MTRR min hole alignment 64MB by Duncan Laurie · 13 years ago
  53. 527fc74 Fix MB calculation in the reporting of the MTRR hole by Duncan Laurie · 13 years ago
  54. 7389fa9 MTRR: add alternate allocation method for odd memory maps by Duncan Laurie · 13 years ago
  55. 67e6c2a Don't re-init EBDA in S3 resume path. by Duncan Laurie · 13 years ago
  56. b4aaaa7 Prepare the BIOS data areas before device init. by Duncan Laurie · 13 years ago
  57. 1d0b1d4 vga_io.c is not needed unless CONFIG_VGA is set by Stefan Reinauer · 13 years ago
  58. bb1177e Allow components smaller than declared size. by Vadim Bendebury · 13 years ago
  59. 8bb7723 Add Kconfig options to enable TSEG and set a size by Duncan Laurie · 13 years ago
  60. 689e31d Make cpuid functions usable when compiled with PIC by Duncan Laurie · 13 years ago
  61. 5d3438d Revamp cbmem.py to use the coreboot tables. by Gabe Black · 13 years ago
  62. 67aa3d6 drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed by Stefan Reinauer · 13 years ago
  63. 5e02bc6 Make PCI CONF2 support a compile time option by Stefan Reinauer · 13 years ago
  64. bf729ba Add more timestamps in coreboot. by Stefan Reinauer · 13 years ago
  65. 10fea92 Fix coreboot makefiles not to produce half baked output. by Vadim Bendebury · 13 years ago
  66. cde7801 Add timestamps for selfboot and acpi wake by Duncan Laurie · 13 years ago
  67. c668af7 Make TPM driver work in rom stage. by Stefan Reinauer · 13 years ago
  68. 3008bbad Add TPM support to coreboot by Stefan Reinauer · 13 years ago
  69. b89a761 Add Google ChromeOS vendorcode directory by Stefan Reinauer · 12 years ago
  70. 00093a8 Add an option to keep the ROM cached after romstage by Stefan Reinauer · 13 years ago
  71. 1afe51a Add native memset() function on x86 by Stefan Reinauer · 13 years ago
  72. 0054afa Add faster, architecture dependent memcpy() by Stefan Reinauer · 13 years ago
  73. 19e7e7d Add infrastructure for global data in the CAR phase of boot by Gabe Black · 13 years ago
  74. 4d04a71 Detect whether the OXPCIE card is really present while in the ROM stage. by Gabe Black · 13 years ago
  75. 1b632af Fix typos in src/console/Kconfig by Stefan Reinauer · 13 years ago
  76. 90dcdd4 Add support for enabling PCIe Common Clock and ASPM by Duncan Laurie · 13 years ago
  77. 22c0468 Refactor publishing CBMEM addresses through coreboot table. by Vadim Bendebury · 13 years ago
  78. 2e43867 Add timestamp table pointer to the coreboot table. by Vadim Bendebury · 13 years ago
  79. b93f74b Introduce utility for parsing CBMEM contents. by Vadim Bendebury · 13 years ago
  80. 3e31600 CBMEM CONSOLE: Enable coreboot CBMEM console. by Vadim Bendebury · 13 years ago
  81. 1078c67 CBMEM CONSOLE: Add code using the new console driver. by Vadim Bendebury · 13 years ago
  82. be25a4d CBMEM CONSOLE: Add CBMEM type for console buffer. by Vadim Bendebury · 13 years ago
  83. 32da8be CBMEM CONSOLE: Add CBMEM console driver implementation. by Vadim Bendebury · 13 years ago
  84. c34b463 CBMEM CONSOLE: Add config option for CBMEM stored console log. by Vadim Bendebury · 13 years ago
  85. f2f9386 Increase CBMEM to accommodate larger console. by Vadim Bendebury · 13 years ago
  86. 654f293 Add cmos helper functions for reading/writing a dword by Duncan Laurie · 13 years ago
  87. 9ec8ed8 selfboot: Allow loading SeaBIOS into a reserved region in the lower 1MB by Stefan Reinauer · 13 years ago
  88. e246b31 Include arch/acpi.h instead of manually adding acpi_slp_type. by Stefan Reinauer · 13 years ago
  89. 6f72d69 Add timestamp collecting to coreboot. by Vadim Bendebury · 13 years ago
  90. 9202473d Add a config flag to enable time stamp collection by Vadim Bendebury · 13 years ago
  91. e186060 Initialize CBMEM early. by Vadim Bendebury · 13 years ago
  92. e6b6aff Introduce config option to initialize CBMEM early. by Vadim Bendebury · 13 years ago
  93. c9da015 Add bifferboard by Rudolf Marek · 12 years ago
  94. ae012486 Add 64KB romchip chip size by Rudolf Marek · 12 years ago
  95. 6b89b4c Add support for RDC R8610 Southbridge by Rudolf Marek · 12 years ago
  96. c0c5ac7 Add the support for RDC R8610 Northbridge by Rudolf Marek · 12 years ago
  97. 1c89e90 Add RDC R8610 PCI IDs. by Rudolf Marek · 12 years ago
  98. 1dd0dda Fix cleaning SeaBIOS from coreboot makefile by Marc Jones · 12 years ago
  99. 6588802 Disable the GDB stub by default by Rudolf Marek · 12 years ago
  100. a01ae62 Fix possible deadlock on SMP stop_this_cpu by Kyösti Mälkki · 12 years ago