Jian Tong | e4d73ec | 2024-05-22 10:43:27 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
| 5 | #include <gpio.h> |
| 6 | |
| 7 | static const struct mb_cfg baseboard_memcfg = { |
| 8 | .type = MEM_TYPE_LP5X, |
| 9 | |
| 10 | /* Leave Rcomp unspecified to use the FSP optimized defaults */ |
| 11 | |
| 12 | /* DQ byte map */ |
| 13 | .lpx_dq_map = { |
| 14 | .ddr0 = { |
| 15 | .dq0 = { 13, 15, 14, 12, 11, 9, 10, 8 }, |
| 16 | .dq1 = { 3, 0, 2, 1, 6, 7, 5, 4 }, |
| 17 | }, |
| 18 | .ddr1 = { |
| 19 | .dq0 = { 2, 0, 1, 3, 6, 4, 7, 5 }, |
| 20 | .dq1 = { 13, 15, 12, 14, 10, 11, 8, 9 }, |
| 21 | }, |
| 22 | .ddr2 = { |
| 23 | .dq0 = { 14, 13, 12, 15, 9, 10, 11, 8 }, |
| 24 | .dq1 = { 4, 6, 7, 5, 1, 2, 0, 3 }, |
| 25 | }, |
| 26 | .ddr3 = { |
| 27 | .dq0 = { 14, 13, 15, 12, 8, 11, 9, 10 }, |
| 28 | .dq1 = { 0, 2, 1, 3, 6, 5, 7, 4 }, |
| 29 | }, |
| 30 | .ddr4 = { |
| 31 | .dq0 = { 8, 11, 10, 9, 14, 15, 13, 12 }, |
| 32 | .dq1 = { 3, 0, 2, 1, 5, 7, 4, 6 }, |
| 33 | }, |
| 34 | .ddr5 = { |
| 35 | .dq0 = { 2, 1, 3, 0, 6, 4, 7, 5 }, |
| 36 | .dq1 = { 12, 13, 15, 14, 10, 9, 8, 11 }, |
| 37 | }, |
| 38 | .ddr6 = { |
| 39 | .dq0 = { 1, 0, 3, 2, 5, 7, 6, 4 }, |
| 40 | .dq1 = { 15, 13, 12, 14, 8, 11, 10, 9 }, |
| 41 | }, |
| 42 | .ddr7 = { |
| 43 | .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6 }, |
| 44 | .dq1 = { 14, 15, 9, 11, 12, 8, 10, 13 }, |
| 45 | }, |
| 46 | }, |
| 47 | |
| 48 | /* DQS CPU<>DRAM map */ |
| 49 | .lpx_dqs_map = { |
| 50 | .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, |
| 51 | .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, |
| 52 | .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, |
| 53 | .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, |
| 54 | .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, |
| 55 | .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, |
| 56 | .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, |
| 57 | .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, |
| 58 | }, |
| 59 | |
| 60 | .lp5x_config = { |
| 61 | .ccc_config = 0xff, |
| 62 | }, |
| 63 | |
| 64 | .LpDdrDqDqsReTraining = 1, |
| 65 | |
| 66 | .ect = 1, /* Early Command Training */ |
| 67 | }; |
| 68 | |
| 69 | const struct mb_cfg *variant_memory_params(void) |
| 70 | { |
| 71 | return &baseboard_memcfg; |
| 72 | } |
| 73 | |
| 74 | int variant_memory_sku(void) |
| 75 | { |
| 76 | /* |
| 77 | * Memory configuration board straps |
| 78 | * MEM_STRAP_0 GPP_S4 |
| 79 | * MEM_STRAP_1 GPP_S5 |
| 80 | * MEM_STRAP_2 GPP_S6 |
| 81 | * MEM_STRAP_3 GPP_S7 |
| 82 | */ |
| 83 | gpio_t spd_gpios[] = { |
| 84 | GPP_S4, |
| 85 | GPP_S5, |
| 86 | GPP_S6, |
| 87 | GPP_S7, |
| 88 | }; |
| 89 | |
| 90 | return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); |
| 91 | } |
| 92 | |
| 93 | bool variant_is_half_populated(void) |
| 94 | { |
| 95 | /* MEM_CH_SEL GPP_S0 */ |
| 96 | return gpio_get(GPP_S0); |
| 97 | } |
| 98 | |
| 99 | void variant_get_spd_info(struct mem_spd *spd_info) |
| 100 | { |
| 101 | spd_info->topo = MEM_TOPO_MEMORY_DOWN; |
| 102 | spd_info->cbfs_index = variant_memory_sku(); |
| 103 | } |