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Marshall Dawsoneecb7942017-09-28 17:32:30 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2017 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
Kyösti Mälkki13f66502019-03-03 08:01:05 +020016#include <arch/io.h>
17#include <device/mmio.h>
Marshall Dawson3a7de792017-11-16 09:14:15 -070018#include <arch/acpi.h>
Marshall Dawsoneecb7942017-09-28 17:32:30 -060019#include <soc/southbridge.h>
20
21void pm_write8(u8 reg, u8 value)
22{
23 write8((void *)(PM_MMIO_BASE + reg), value);
24}
25
26u8 pm_read8(u8 reg)
27{
28 return read8((void *)(PM_MMIO_BASE + reg));
29}
30
31void pm_write16(u8 reg, u16 value)
32{
33 write16((void *)(PM_MMIO_BASE + reg), value);
34}
35
36u16 pm_read16(u8 reg)
37{
38 return read16((void *)(PM_MMIO_BASE + reg));
39}
40
Raul E Rangel6b0fc802018-08-02 15:56:34 -060041void misc_write32(u8 reg, u32 value)
42{
43 write32((void *)(MISC_MMIO_BASE + reg), value);
44}
45
46u32 misc_read32(u8 reg)
47{
48 return read32((void *)(MISC_MMIO_BASE + reg));
49}
50
Marshall Dawsoneecb7942017-09-28 17:32:30 -060051void pm_write32(u8 reg, u32 value)
52{
53 write32((void *)(PM_MMIO_BASE + reg), value);
54}
55
56u32 pm_read32(u8 reg)
57{
58 return read32((void *)(PM_MMIO_BASE + reg));
59}
60
Richard Spiegele6f7c8e2018-10-30 13:24:44 -070061u8 acpi_read8(u8 reg)
62{
63 return read8((void *)(ACPI_REG_MMIO_BASE + reg));
64}
65
66u16 acpi_read16(u8 reg)
67{
68 return read16((void *)(ACPI_REG_MMIO_BASE + reg));
69}
70
71u32 acpi_read32(u8 reg)
72{
73 return read32((void *)(ACPI_REG_MMIO_BASE + reg));
74}
75
76void acpi_write8(u8 reg, u8 value)
77{
78 write8((void *)(ACPI_REG_MMIO_BASE + reg), value);
79}
80
81void acpi_write16(u8 reg, u16 value)
82{
83 write16((void *)(ACPI_REG_MMIO_BASE + reg), value);
84}
85
86void acpi_write32(u8 reg, u32 value)
87{
88 write32((void *)(ACPI_REG_MMIO_BASE + reg), value);
89}
90
Marshall Dawsoneecb7942017-09-28 17:32:30 -060091void smi_write32(uint8_t offset, uint32_t value)
92{
93 write32((void *)(APU_SMI_BASE + offset), value);
94}
95
96uint32_t smi_read32(uint8_t offset)
97{
98 return read32((void *)(APU_SMI_BASE + offset));
99}
100
101uint16_t smi_read16(uint8_t offset)
102{
103 return read16((void *)(APU_SMI_BASE + offset));
104}
105
106void smi_write16(uint8_t offset, uint16_t value)
107{
108 write16((void *)(APU_SMI_BASE + offset), value);
109}
Marshall Dawson813462e2017-10-04 15:05:17 -0600110
Marc Jonese8e72bd2017-10-04 22:12:31 -0600111uint8_t smi_read8(uint8_t offset)
112{
113 return read8((void *)(APU_SMI_BASE + offset));
114}
115
116void smi_write8(uint8_t offset, uint8_t value)
117{
118 write8((void *)(APU_SMI_BASE + offset), value);
119}
120
Marshall Dawsona89d19a2017-11-28 17:51:29 -0700121uint8_t biosram_read8(uint8_t offset)
122{
Marshall Dawson50cc53d2018-01-24 21:00:55 -0700123 return read8((void *)(BIOSRAM_MMIO_BASE + offset));
Marshall Dawsona89d19a2017-11-28 17:51:29 -0700124}
125
126void biosram_write8(uint8_t offset, uint8_t value)
127{
Marshall Dawson50cc53d2018-01-24 21:00:55 -0700128 write8((void *)(BIOSRAM_MMIO_BASE + offset), value);
Marshall Dawsona89d19a2017-11-28 17:51:29 -0700129}
130
Marshall Dawson50cc53d2018-01-24 21:00:55 -0700131/* BiosRam may only be accessed a byte at a time */
Marshall Dawsona89d19a2017-11-28 17:51:29 -0700132uint16_t biosram_read16(uint8_t offset)
133{
134 int i;
135 uint16_t value = 0;
136 for (i = sizeof(value) - 1 ; i >= 0 ; i--)
137 value = (value << 8) | biosram_read8(offset + i);
138 return value;
139}
140
141uint32_t biosram_read32(uint8_t offset)
142{
143 uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16;
144 return value | biosram_read16(offset);
145}
146
147void biosram_write16(uint8_t offset, uint16_t value)
148{
149 int i;
150 for (i = 0 ; i < sizeof(value) ; i++) {
151 biosram_write8(offset + i, value & 0xff);
152 value >>= 8;
153 }
154}
155
156void biosram_write32(uint8_t offset, uint32_t value)
157{
158 int i;
159 for (i = 0 ; i < sizeof(value) ; i++) {
160 biosram_write8(offset + i, value & 0xff);
161 value >>= 8;
162 }
163}
164
Marshall Dawson813462e2017-10-04 15:05:17 -0600165uint16_t pm_acpi_pm_cnt_blk(void)
166{
167 return pm_read16(PM1_CNT_BLK);
168}
Marshall Dawson07568802017-11-08 15:43:06 -0700169
170uint16_t pm_acpi_pm_evt_blk(void)
171{
172 return pm_read16(PM_EVT_BLK);
173}
Marc Jones7654f862017-12-01 17:17:43 -0700174
175void xhci_pm_write8(uint8_t reg, uint8_t value)
176{
177 write8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value);
178}
179
180uint8_t xhci_pm_read8(uint8_t reg)
181{
182 return read8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg));
183}
184
185void xhci_pm_write16(uint8_t reg, uint16_t value)
186{
187 write16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value);
188}
189
190uint16_t xhci_pm_read16(uint8_t reg)
191{
192 return read16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg));
193}
194
195void xhci_pm_write32(uint8_t reg, uint32_t value)
196{
197 write32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value);
198}
199
200uint32_t xhci_pm_read32(uint8_t reg)
201{
202 return read32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg));
203}
Marshall Dawson3a7de792017-11-16 09:14:15 -0700204
Richard Spiegelb40e1932018-10-24 12:51:21 -0700205void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value)
206{
207 write8((void *)(mmio + reg), value);
208}
209
210uint8_t smbus_read8(uint32_t mmio, uint8_t reg)
211{
212 return read8((void *)(mmio + reg));
213}
214
Marshall Dawson3a7de792017-11-16 09:14:15 -0700215int acpi_get_sleep_type(void)
216{
217 return acpi_sleep_from_pm1(inw(pm_acpi_pm_cnt_blk()));
218}
Marc Jonesfa650f52018-02-08 23:19:29 -0700219
220void save_uma_size(uint32_t size)
221{
222 biosram_write32(BIOSRAM_UMA_SIZE, size);
223}
224
225void save_uma_base(uint64_t base)
226{
227 biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base);
228 biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32));
229}
230
231uint32_t get_uma_size(void)
232{
233 return biosram_read32(BIOSRAM_UMA_SIZE);
234}
235
236uint64_t get_uma_base(void)
237{
238 uint64_t base;
239 base = biosram_read32(BIOSRAM_UMA_BASE);
240 base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32);
241 return base;
242}