blob: 585c0154cc3623d94c4d967f301ecf72d538701e [file] [log] [blame]
Marc Jones2d79f162017-05-22 21:35:16 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015, 2016 Advanced Micro Devices, Inc.
5 * Copyright (C) 2013 Sage Electronic Engineering, LLC
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17/*
Elyes HAOUAS6d19a202018-11-22 11:15:29 +010018 * #include <arch/acpi.h>
19DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
Marc Jonese9352a12017-04-14 12:19:16 -060020 *{
21 * #include "routing.asl"
22 *}
23 */
Marc Jones2d79f162017-05-22 21:35:16 -060024
25/* Routing is in System Bus scope */
Marc Jonese9352a12017-04-14 12:19:16 -060026Name (PR0, Package()
27{
Marc Jones2d79f162017-05-22 21:35:16 -060028 /* NB devices */
29 /* Bus 0, Dev 0 - F15 Host Controller */
30
31 /* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */
32 /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
Richard Spiegel48e07492018-04-03 08:51:48 -070033 Package() { 0x0001FFFF, 0, INTG, 0 },
34 Package() { 0x0001FFFF, 1, INTH, 0 },
35 Package() { 0x0001FFFF, 2, INTE, 0 },
36 Package() { 0x0001FFFF, 3, INTF, 0 },
Marc Jones2d79f162017-05-22 21:35:16 -060037
38
39 /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
Richard Spiegel48e07492018-04-03 08:51:48 -070040 Package() { 0x0002FFFF, 0, INTH, 0 },
41 Package() { 0x0002FFFF, 1, INTA, 0 },
42 Package() { 0x0002FFFF, 2, INTB, 0 },
43 Package() { 0x0002FFFF, 3, INTC, 0 },
Marc Jones2d79f162017-05-22 21:35:16 -060044
45 /* FCH devices */
46 /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */
Marc Jonese9352a12017-04-14 12:19:16 -060047 Package() { 0x0014FFFF, 0, INTA, 0 },
48 Package() { 0x0014FFFF, 1, INTB, 0 },
49 Package() { 0x0014FFFF, 2, INTC, 0 },
50 Package() { 0x0014FFFF, 3, INTD, 0 },
Marc Jones2d79f162017-05-22 21:35:16 -060051
52 /* Bus 0, Dev 18 Func 0 - USB: EHCI */
Marc Jonese9352a12017-04-14 12:19:16 -060053 Package() { 0x0012FFFF, 0, INTC, 0 },
Marc Jones2d79f162017-05-22 21:35:16 -060054
55 /* Bus 0, Dev 10 Func 0 - USB: xHCI */
Marc Jonese9352a12017-04-14 12:19:16 -060056 Package() { 0x0010FFFF, 0, INTC, 0 },
Marc Jones2d79f162017-05-22 21:35:16 -060057
58 /* Bus 0, Dev 17 - SATA controller */
Marc Jonese9352a12017-04-14 12:19:16 -060059 Package() { 0x0011FFFF, 0, INTD, 0 },
Marc Jones2d79f162017-05-22 21:35:16 -060060
61})
62
Marc Jonese9352a12017-04-14 12:19:16 -060063Name (APR0, Package()
64{
Marc Jones2d79f162017-05-22 21:35:16 -060065 /* NB devices in APIC mode */
66 /* Bus 0, Dev 0 - F15 Host Controller */
67
68 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
Richard Spiegel48e07492018-04-03 08:51:48 -070069 /* IOAPIC2BASE + (group * 4) == 24 + (1 * 4), CDAB swizzle */
70 Package() { 0x0001FFFF, 0, 0, 30 },
71 Package() { 0x0001FFFF, 1, 0, 31 },
72 Package() { 0x0001FFFF, 1, 0, 28 },
73 Package() { 0x0001FFFF, 1, 0, 29 },
Marc Jones2d79f162017-05-22 21:35:16 -060074
75 /* Bus 0, Dev 2 - PCIe Bridges */
Richard Spiegel48e07492018-04-03 08:51:48 -070076 /* IOAPIC2BASE + 23 */
77 Package() { 0x0002FFFF, 0, 0, 47 },
78 Package() { 0x0002FFFF, 1, 0, 48 },
79 Package() { 0x0002FFFF, 2, 0, 49 },
80 Package() { 0x0002FFFF, 3, 0, 50 },
Marc Jones2d79f162017-05-22 21:35:16 -060081
82 /* SB devices in APIC mode */
83 /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */
Marc Jonese9352a12017-04-14 12:19:16 -060084 Package() { 0x0014FFFF, 0, 0, 16 },
85 Package() { 0x0014FFFF, 1, 0, 17 },
86 Package() { 0x0014FFFF, 2, 0, 18 },
87 Package() { 0x0014FFFF, 3, 0, 19 },
Marc Jones2d79f162017-05-22 21:35:16 -060088
89 /* Bus 0, Dev 18 Func 0 - USB: EHCI */
Marc Jonese9352a12017-04-14 12:19:16 -060090 Package() { 0x0012FFFF, 0, 0, 18 },
Marc Jones2d79f162017-05-22 21:35:16 -060091
92 /* Bus 0, Dev 10 Func 0 - USB: xHCI */
Marc Jonese9352a12017-04-14 12:19:16 -060093 Package() { 0x0010FFFF, 0, 0, 18},
Marc Jones2d79f162017-05-22 21:35:16 -060094
95 /* Bus 0, Dev 17 - SATA controller */
Marc Jonese9352a12017-04-14 12:19:16 -060096 Package() { 0x0011FFFF, 0, 0, 19 },
Marc Jones2d79f162017-05-22 21:35:16 -060097})
98
99
100/* GPP 0 */
Marc Jonese9352a12017-04-14 12:19:16 -0600101Name (PS4, Package()
102{
103 Package() { 0x0000FFFF, 0, INTA, 0 },
104 Package() { 0x0000FFFF, 1, INTB, 0 },
105 Package() { 0x0000FFFF, 2, INTC, 0 },
106 Package() { 0x0000FFFF, 3, INTD, 0 },
Marc Jones2d79f162017-05-22 21:35:16 -0600107})
Marc Jonese9352a12017-04-14 12:19:16 -0600108Name (APS4, Package()
Richard Spiegel48e07492018-04-03 08:51:48 -0700109{ /* IOAPIC2BASE + (group * 4) == 24 + (0 * 4), no swizzle */
Marc Jones2d79f162017-05-22 21:35:16 -0600110 /* PCIe slot - Hooked to PCIe slot 4 */
Marc Jonese9352a12017-04-14 12:19:16 -0600111 Package() { 0x0000FFFF, 0, 0, 24 },
112 Package() { 0x0000FFFF, 1, 0, 25 },
113 Package() { 0x0000FFFF, 2, 0, 26 },
114 Package() { 0x0000FFFF, 3, 0, 27 },
Marc Jones2d79f162017-05-22 21:35:16 -0600115})
116
117/* GPP 1 */
Marc Jonese9352a12017-04-14 12:19:16 -0600118Name (PS5, Package()
119{
Richard Spiegel48e07492018-04-03 08:51:48 -0700120 Package() { 0x0000FFFF, 0, INTA, 0 },
121 Package() { 0x0000FFFF, 1, INTB, 0 },
122 Package() { 0x0000FFFF, 2, INTC, 0 },
123 Package() { 0x0000FFFF, 3, INTD, 0 },
Marc Jones2d79f162017-05-22 21:35:16 -0600124})
Marc Jonese9352a12017-04-14 12:19:16 -0600125Name (APS5, Package()
Richard Spiegel48e07492018-04-03 08:51:48 -0700126{ /* IOAPIC2BASE + (group * 4) == 24 + (2 * 4), no swizzle */
Marc Jonese9352a12017-04-14 12:19:16 -0600127 Package() { 0x0000FFFF, 0, 0, 32 },
128 Package() { 0x0000FFFF, 1, 0, 33 },
129 Package() { 0x0000FFFF, 2, 0, 34 },
130 Package() { 0x0000FFFF, 3, 0, 35 },
Marc Jones2d79f162017-05-22 21:35:16 -0600131})
132
Richard Spiegel48e07492018-04-03 08:51:48 -0700133/* GPP 2 */
134Name (PS6, Package()
135{
136 Package() { 0x0000FFFF, 0, INTA, 0 },
137 Package() { 0x0000FFFF, 1, INTB, 0 },
138 Package() { 0x0000FFFF, 2, INTC, 0 },
139 Package() { 0x0000FFFF, 3, INTD, 0 },
140})
141Name (APS6, Package()
142{ /* IOAPIC2BASE + (group * 4) == 24 + (4 * 4), no swizzle */
143 Package() { 0x0000FFFF, 0, 0, 40 },
144 Package() { 0x0000FFFF, 1, 0, 41 },
145 Package() { 0x0000FFFF, 2, 0, 42 },
146 Package() { 0x0000FFFF, 3, 0, 43 },
147})
148
Marc Jones2d79f162017-05-22 21:35:16 -0600149/* GPP 3 */
Marc Jonese9352a12017-04-14 12:19:16 -0600150Name (PS7, Package()
151{
Richard Spiegel48e07492018-04-03 08:51:48 -0700152 Package() { 0x0000FFFF, 0, INTA, 0 },
153 Package() { 0x0000FFFF, 1, INTB, 0 },
154 Package() { 0x0000FFFF, 2, INTC, 0 },
155 Package() { 0x0000FFFF, 3, INTD, 0 },
Marc Jones2d79f162017-05-22 21:35:16 -0600156})
Marc Jonese9352a12017-04-14 12:19:16 -0600157Name (APS7, Package()
Richard Spiegel48e07492018-04-03 08:51:48 -0700158{ /* IOAPIC2BASE + (group * 4) == 24 + (6 * 4), no swizzle */
159 Package() { 0x0000FFFF, 0, 0, 48 },
160 Package() { 0x0000FFFF, 1, 0, 49 },
161 Package() { 0x0000FFFF, 2, 0, 50 },
162 Package() { 0x0000FFFF, 3, 0, 51 },
Marc Jones2d79f162017-05-22 21:35:16 -0600163})
164
165/* GPP 4 */
166Name(PS8, Package(){
167 Package(){0x0000FFFF, 0, INTA, 0 },
168 Package(){0x0000FFFF, 1, INTB, 0 },
169 Package(){0x0000FFFF, 2, INTC, 0 },
170 Package(){0x0000FFFF, 3, INTD, 0 },
171})
Marc Jonese9352a12017-04-14 12:19:16 -0600172Name (APS8, Package()
Richard Spiegel48e07492018-04-03 08:51:48 -0700173{ /* IOAPIC2BASE + (group * 4) == 24 + (0 * 4), DABC swizzle */
174 Package() { 0x0000FFFF, 0, 0, 27 },
175 Package() { 0x0000FFFF, 1, 0, 24 },
176 Package() { 0x0000FFFF, 2, 0, 25 },
177 Package() { 0x0000FFFF, 3, 0, 26 },
Marc Jones2d79f162017-05-22 21:35:16 -0600178})