Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 1 | config SOC_INTEL_CANNONLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Cannonlake support |
| 5 | |
| 6 | if SOC_INTEL_CANNONLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 11 | select ARCH_BOOTBLOCK_X86_32 |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 12 | select ARCH_RAMSTAGE_X86_32 |
| 13 | select ARCH_ROMSTAGE_X86_32 |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 14 | select ARCH_VERSTAGE_X86_32 |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 15 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 16 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 17 | select C_ENVIRONMENT_BOOTBLOCK |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 18 | select COMMON_FADT |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 19 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Nick Vaccaro | 69b5cdb | 2017-08-29 19:25:23 -0700 | [diff] [blame] | 20 | select GENERIC_GPIO_LIB |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 21 | select HAVE_HARD_RESET |
| 22 | select HAVE_INTEL_FIRMWARE |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 23 | select HAVE_MONOTONIC_TIMER |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 24 | select INTEL_CAR_NEM_ENHANCED |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 25 | select PARALLEL_MP |
| 26 | select PARALLEL_MP_AP_WORK |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 27 | select PLATFORM_USES_FSP2_0 |
Lijian Zhao | 8465a81 | 2017-07-11 12:33:22 -0700 | [diff] [blame] | 28 | select POSTCAR_CONSOLE |
| 29 | select POSTCAR_STAGE |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 30 | select REG_SCRIPT |
Lijian Zhao | a77c68a | 2017-07-18 18:14:42 -0700 | [diff] [blame] | 31 | select RELOCATABLE_RAMSTAGE |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 32 | select SMP |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 33 | select SOC_INTEL_COMMON |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 34 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 35 | select SOC_INTEL_COMMON_BLOCK |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 36 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 37 | select SOC_INTEL_COMMON_BLOCK_CAR |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 38 | select SOC_INTEL_COMMON_BLOCK_CPU |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 39 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 40 | select SOC_INTEL_COMMON_BLOCK_CSE |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 41 | select SOC_INTEL_COMMON_BLOCK_FAST_SPI |
Andrey Petrov | c854b49 | 2017-06-05 14:10:17 -0700 | [diff] [blame] | 42 | select SOC_INTEL_COMMON_BLOCK_GPIO |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 43 | select SOC_INTEL_COMMON_BLOCK_GSPI |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 44 | select SOC_INTEL_COMMON_BLOCK_LPSS |
| 45 | select SOC_INTEL_COMMON_BLOCK_PCR |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 46 | select SOC_INTEL_COMMON_BLOCK_PMC |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_BLOCK_RTC |
| 48 | select SOC_INTEL_COMMON_BLOCK_SA |
| 49 | select SOC_INTEL_COMMON_BLOCK_SMBUS |
Brandon Breitenstein | ae15486 | 2017-08-01 11:32:06 -0700 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 51 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_TIMER |
| 53 | select SOC_INTEL_COMMON_BLOCK_UART |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_SPI_FLASH_PROTECT |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_RESET |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 56 | select SUPPORT_CPU_UCODE_IN_CBFS |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 57 | select TSC_CONSTANT_RATE |
| 58 | select TSC_MONOTONIC_TIMER |
| 59 | select UDELAY_TSC |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 60 | |
| 61 | config UART_DEBUG |
| 62 | bool "Enable UART debug port." |
| 63 | default y |
| 64 | select CONSOLE_SERIAL |
| 65 | select BOOTBLOCK_CONSOLE |
| 66 | select DRIVERS_UART |
Lijian Zhao | d37ebdd | 2017-08-30 20:54:16 -0700 | [diff] [blame] | 67 | select DRIVERS_UART_8250MEM_32 |
| 68 | select NO_UART_ON_SUPERIO |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 69 | |
Subrata Banik | ce4c9ec | 2017-08-14 13:23:54 +0530 | [diff] [blame] | 70 | config UART_FOR_CONSOLE |
| 71 | int "Index for LPSS UART port to use for console" |
| 72 | default 2 if DRIVERS_UART_8250MEM |
Subrata Banik | b045d4c | 2017-08-30 11:47:32 +0530 | [diff] [blame] | 73 | default 0 |
Subrata Banik | ce4c9ec | 2017-08-14 13:23:54 +0530 | [diff] [blame] | 74 | help |
| 75 | Index for LPSS UART port to use for console: |
| 76 | 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 |
| 77 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 78 | config DCACHE_RAM_BASE |
| 79 | default 0xfef00000 |
| 80 | |
| 81 | config DCACHE_RAM_SIZE |
| 82 | default 0x40000 |
| 83 | help |
| 84 | The size of the cache-as-ram region required during bootblock |
| 85 | and/or romstage. |
| 86 | |
| 87 | config DCACHE_BSP_STACK_SIZE |
| 88 | hex |
| 89 | default 0x4000 |
| 90 | help |
| 91 | The amount of anticipated stack usage in CAR by bootblock and |
| 92 | other stages. |
| 93 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 94 | config IED_REGION_SIZE |
| 95 | hex |
| 96 | default 0x400000 |
| 97 | |
Pratik Prajapati | c8c741d | 2017-08-29 11:38:42 -0700 | [diff] [blame] | 98 | config MAX_ROOT_PORTS |
| 99 | int |
| 100 | default 24 |
| 101 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 102 | config SMM_TSEG_SIZE |
| 103 | hex |
| 104 | default 0x800000 |
| 105 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 106 | config PCR_BASE_ADDRESS |
| 107 | hex |
| 108 | default 0xfd000000 |
| 109 | help |
| 110 | This option allows you to select MMIO Base Address of sideband bus. |
| 111 | |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 112 | config CPU_BCLK_MHZ |
| 113 | int |
| 114 | default 100 |
| 115 | |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 116 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 117 | int |
| 118 | default 3 |
| 119 | |
Lijian Zhao | 8465a81 | 2017-07-11 12:33:22 -0700 | [diff] [blame] | 120 | # Clock divider parameters for 115200 baud rate |
| 121 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 122 | hex |
| 123 | default 0x30 |
| 124 | |
| 125 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 126 | hex |
| 127 | default 0xc35 |
| 128 | |
Lijian Zhao | 6d7063c | 2017-08-29 17:26:48 -0700 | [diff] [blame] | 129 | config CHROMEOS |
| 130 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 131 | |
| 132 | config VBOOT |
| 133 | select VBOOT_SEPARATE_VERSTAGE |
| 134 | select VBOOT_OPROM_MATTERS |
| 135 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
| 136 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 137 | select VBOOT_VBNV_CMOS |
| 138 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 139 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 140 | endif |