Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 15 | #include <arch/io.h> |
| 16 | #include <device/mmio.h> |
| 17 | #include <bootstate.h> |
| 18 | #include <console/console.h> |
| 19 | #include <console/post_codes.h> |
| 20 | #include <cpu/x86/smm.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <intelblocks/lpc_lib.h> |
| 23 | #include <intelblocks/pcr.h> |
| 24 | #include <intelblocks/tco.h> |
| 25 | #include <intelblocks/thermal.h> |
| 26 | #include <reg_script.h> |
| 27 | #include <spi-generic.h> |
| 28 | #include <soc/p2sb.h> |
| 29 | #include <soc/pci_devs.h> |
| 30 | #include <soc/pcr_ids.h> |
| 31 | #include <soc/pm.h> |
| 32 | #include <soc/smbus.h> |
| 33 | #include <soc/soc_chip.h> |
| 34 | #include <soc/systemagent.h> |
| 35 | |
| 36 | #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ |
| 37 | #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ |
| 38 | #define CAM_CLK_EN (1 << 1) |
| 39 | #define MIPI_CLK (1 << 0) |
| 40 | #define HDPLL_CLK (0 << 0) |
| 41 | |
| 42 | static void pch_enable_isclk(void) |
| 43 | { |
| 44 | pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); |
| 45 | pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK); |
| 46 | } |
| 47 | |
| 48 | static void pch_handle_sideband(config_t *config) |
| 49 | { |
| 50 | if (config->pch_isclk) |
| 51 | pch_enable_isclk(); |
| 52 | } |
| 53 | |
| 54 | static void pch_finalize(void) |
| 55 | { |
| 56 | uint32_t reg32; |
| 57 | uint8_t *pmcbase; |
| 58 | config_t *config; |
| 59 | uint8_t reg8; |
| 60 | |
| 61 | /* TCO Lock down */ |
| 62 | tco_lockdown(); |
| 63 | |
| 64 | /* TODO: Add Thermal Configuration */ |
| 65 | |
| 66 | /* |
| 67 | * Disable ACPI PM timer based on dt policy |
| 68 | * |
| 69 | * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. |
| 70 | * Disabling ACPI PM timer also switches off TCO |
| 71 | * |
| 72 | * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is |
| 73 | * just required to get to chip config. PCH_DEV_PMC is hidden by this |
| 74 | * point and hence removed from the root bus. pcidev_path_on_root thus |
| 75 | * returns NULL for PCH_DEV_PMC device. |
| 76 | */ |
| 77 | config = config_of_soc(); |
| 78 | pmcbase = pmc_mmio_regs(); |
| 79 | if (config->PmTimerDisabled) { |
| 80 | reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); |
| 81 | reg8 |= (1 << 1); |
| 82 | write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); |
| 83 | } |
| 84 | |
| 85 | /* Disable XTAL shutdown qualification for low power idle. */ |
| 86 | if (config->s0ix_enable) { |
| 87 | reg32 = read32(pmcbase + CPPMVRIC); |
| 88 | reg32 |= XTALSDQDIS; |
| 89 | write32(pmcbase + CPPMVRIC, reg32); |
| 90 | } |
| 91 | |
| 92 | pch_handle_sideband(config); |
| 93 | |
| 94 | pmc_clear_pmcon_sts(); |
| 95 | } |
| 96 | |
| 97 | static void soc_finalize(void *unused) |
| 98 | { |
| 99 | printk(BIOS_DEBUG, "Finalizing chipset.\n"); |
| 100 | |
| 101 | pch_finalize(); |
| 102 | |
| 103 | printk(BIOS_DEBUG, "Finalizing SMM.\n"); |
| 104 | outb(APM_CNT_FINALIZE, APM_CNT); |
| 105 | |
| 106 | /* Indicate finalize step with post code */ |
| 107 | post_code(POST_OS_BOOT); |
| 108 | } |
| 109 | |
| 110 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); |
| 111 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); |