blob: d091148ed8e3a7a8b538115d3e02e405bc0cc431 [file] [log] [blame]
Eric Biedermandbec2d42004-10-21 10:44:08 +00001- 1.1.7
2 - The configuration language has been cleaned up. No more link keyword.
3 - Everything is now in the device tree.
4 - The static and dynamic device trees have been unified
5 - Support for setting the pci subsystem vendor and pci subsystem device has been added.
6 - 64bit resource support
7 - Generic smbus support
Eric Biederman5cd81732004-03-11 15:01:31 +00008- 1.1.6
9 - pnp/superio devices are now handled cleanly with very little code
10 - Initial support for finding x86 BIST errors
11 - static resource assignments can now be specified in Config.lb
12 - special VGA I/O decode now should work
13 - added generic PCI error reporting enables
14 - build_opt_tbl now generates a header that allows cmos settings to
15 be read from romcc compiled code.
16 - split IORESOURCE_SET into IORESOURCE_ASSIGNED and IORESOURCE_STORED
17 - romcc now gracesfully handles function pointers instead of dying mysteriously
18 - First regression test in amdk8/raminit_test
Eric Biederman83b991a2003-10-11 06:20:25 +000019- 1.1.5
20 - O2, enums, and switch statements work in romcc
21 - Support for compiling romcc on non x86 platforms
22 - new romc options -msse and -mmmx for specifying extra registers to use
23 - Bug fixes to device the device disable/enable framework and an amd8111 implementation
24 - Move the link specification to the chip specification instead of the path
25 - Allow specifying devices with internal bridges.
26 - Initial via epia support
27 - Opteron errata fixes
Eric Biederman0ac6b412003-09-02 17:16:48 +000028- 1.1.4
29 Major restructuring of hypertransport handling.
30 Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically
31 Updates to hard_reset handling when resetting because of the need to change hypertransport link
32 speeds and widths.
33 (a) No longer assume the boot is good just because we get to a hard reset point.
34 (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the
35 boot counter.
36 Updates to arima/hdama mptable so it tracks the new bus numbers
Eric Biedermane9a271e32003-09-02 03:36:25 +000037- 1.1.3
38 Major update of the dyanmic device tree to so it can handle
39 * subtractive resources
40 * merging with the static device tree
41 * more device types than just pci
Eric Biederman30e143a2003-09-01 23:45:32 +000042- 1.1.2
43 Add back in the hard_reset method from freebios1 this allows generic
Eric Biedermand4c14522003-09-01 23:47:37 +000044 code to reset the box.
45 Update the hypertransport setup code to automatically optimize
46 hypertransport link widths and frequencies, and to call hard_reset
47 if necessary for the changes to go into effect.
Eric Biederman9bdb4602003-09-01 23:17:58 +000048- 1.1.1
49 Updates to the new configuration system so it works more reliably
50 Removed a bunch of unused configuration variables
51 Removed a bunch of unused assembly code
52- 1.1.0
53 A whole bunch of random ppc and opteron work we never put a good label on
Eric Biederman77d1a832003-04-15 00:44:05 +000054- 1.1.0
55Intial development release of LinuxBIOS.
56Everything is thrown overboard and will be reincluded as necessary so we can
57get rid of the legacy baggage. Since LinuxBIOS was started we have developed
58some better techniques for some things, but we still hang on to the old ways
59because some ports that we want not to break depend on them. So we preserve
60them by preserve the 1.0.x series and keeping only the best practices for
61the 1.1.x series. When there is a stable port this code base will
62become LinuxBIOS 2.0.x and the core will become frozen.
63