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Siyuan Wang80cf7d52013-07-09 17:42:43 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Siyuan Wang80cf7d52013-07-09 17:42:43 +080014 */
15
16#include <stdint.h>
Siyuan Wang80cf7d52013-07-09 17:42:43 +080017#include <device/pci_def.h>
Siyuan Wang80cf7d52013-07-09 17:42:43 +080018#include <arch/io.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020019#include <device/pci_ops.h>
Kyösti Mälkkie912d932016-12-20 06:43:44 +020020#include <northbridge/amd/agesa/state_machine.h>
Edward O'Callaghan77757c22015-01-04 21:33:39 +110021#include <southbridge/amd/agesa/hudson/hudson.h>
Siyuan Wang80cf7d52013-07-09 17:42:43 +080022
Kyösti Mälkkie912d932016-12-20 06:43:44 +020023void board_BeforeAgesa(struct sysinfo *cb)
Siyuan Wang80cf7d52013-07-09 17:42:43 +080024{
Kyösti Mälkkie912d932016-12-20 06:43:44 +020025 int i;
Siyuan Wang80cf7d52013-07-09 17:42:43 +080026 u32 val;
Siyuan Wang80cf7d52013-07-09 17:42:43 +080027
28 /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
29 * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
30 * even though the register is not documented in the Kabini BKDG.
31 * Otherwise the serial output is bad code.
32 */
33 outb(0xD2, 0xcd6);
34 outb(0x00, 0xcd7);
35
Kyösti Mälkkie912d932016-12-20 06:43:44 +020036 /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
37 outb(0xea, 0xcd6);
38 outb(0x1, 0xcd7);
39
Kyösti Mälkki88ff8b52014-11-21 17:40:37 +020040 /* Set LPC decode enables. */
41 pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
42 pci_write_config32(dev, 0x44, 0xff03ffd5);
43
Siyuan Wang80cf7d52013-07-09 17:42:43 +080044 hudson_lpc_port80();
45
Siyuan Wang80cf7d52013-07-09 17:42:43 +080046 /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
Kyösti Mälkkie912d932016-12-20 06:43:44 +020047 for (i = 0; i < 200000; i++)
Siyuan Wang80cf7d52013-07-09 17:42:43 +080048 val = inb(0xcd6);
Siyuan Wang80cf7d52013-07-09 17:42:43 +080049}