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Siyuan Wang80cf7d52013-07-09 17:42:43 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Siyuan Wang80cf7d52013-07-09 17:42:43 +080014 */
15
Siyuan Wang80cf7d52013-07-09 17:42:43 +080016#include <arch/smp/mpspec.h>
17#include <device/pci.h>
18#include <arch/io.h>
Kyösti Mälkkib4261072014-07-22 10:24:20 +030019#include <arch/ioapic.h>
Siyuan Wang80cf7d52013-07-09 17:42:43 +080020#include <string.h>
21#include <stdint.h>
Siyuan Wang80cf7d52013-07-09 17:42:43 +080022#include <cpu/x86/lapic.h>
Elyes HAOUAS4ad14462018-06-16 18:29:33 +020023#include <southbridge/amd/agesa/hudson/hudson.h>
Siyuan Wang80cf7d52013-07-09 17:42:43 +080024
Siyuan Wang80cf7d52013-07-09 17:42:43 +080025u8 picr_data[0x54] = {
26 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
27 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
28 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
29 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
31 0x03,0x04,0x05,0x07
32};
33u8 intr_data[0x54] = {
34 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
35 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
36 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
37 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
38 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
39 0x10,0x11,0x12,0x13
40};
41
Martin Rothad0f4852019-10-23 21:41:43 -060042static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
Siyuan Wang80cf7d52013-07-09 17:42:43 +080043{
44 mc->mpc_length += length;
45 mc->mpc_entry_count++;
46}
47
48static void my_smp_write_bus(struct mp_config_table *mc,
49 unsigned char id, const char *bustype)
50{
51 struct mpc_config_bus *mpc;
52 mpc = smp_next_mpc_entry(mc);
53 memset(mpc, '\0', sizeof(*mpc));
54 mpc->mpc_type = MP_BUS;
55 mpc->mpc_busid = id;
56 memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
57 smp_add_mpc_entry(mc, sizeof(*mpc));
58}
59
60static void *smp_write_config_table(void *v)
61{
62 struct mp_config_table *mc;
63 int bus_isa;
Siyuan Wang80cf7d52013-07-09 17:42:43 +080064 u8 byte;
65
Kyösti Mälkkib4261072014-07-22 10:24:20 +030066 /*
67 * By the time this function gets called, the IOAPIC registers
68 * have been written so they can be read to get the correct
69 * APIC ID and Version
70 */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080071 u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
72 u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
Kyösti Mälkkib4261072014-07-22 10:24:20 +030073
Siyuan Wang80cf7d52013-07-09 17:42:43 +080074 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
75
76 mptable_init(mc, LOCAL_APIC_ADDR);
77 memcpy(mc->mpc_oem, "AMD ", 8);
78
79 smp_write_processors(mc);
80
Siyuan Wang80cf7d52013-07-09 17:42:43 +080081 //mptable_write_buses(mc, NULL, &bus_isa);
82 my_smp_write_bus(mc, 0, "PCI ");
83 my_smp_write_bus(mc, 1, "PCI ");
84 bus_isa = 0x02;
85 my_smp_write_bus(mc, bus_isa, "ISA ");
86
87 /* I/O APICs: APIC ID Version State Address */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080088 smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
Siyuan Wang80cf7d52013-07-09 17:42:43 +080089
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080090 smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
Siyuan Wang80cf7d52013-07-09 17:42:43 +080091 /* PIC IRQ routine */
92 for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
93 outb(byte, 0xC00);
94 outb(picr_data[byte], 0xC01);
95 }
96
97 /* APIC IRQ routine */
98 for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
99 outb(byte | 0x80, 0xC00);
100 outb(intr_data[byte], 0xC01);
101 }
102#if 0
103 outb(0x0B, 0xCD6);
104 outb(0x02, 0xCD7);
105
106 outb(0x50, 0xCD6);
107 outb(0x1F, 0xCD7);
108
109 outb(0x48, 0xCD6);
110 outb(0xF2, 0xCD7);
111
112 //outb(0xBE, 0xCD6);
113 //outb(0x52, 0xCD7);
114
115 outb(0xED, 0xCD6);
116 outb(0x17, 0xCD7);
117
118 *(volatile u8 *) (0xFED80D00 + 0x31) = 2;
119 *(volatile u8 *) (0xFED80D00 + 0x32) = 2;
120 *(volatile u8 *) (0xFED80D00 + 0x33) = 2;
121 *(volatile u8 *) (0xFED80D00 + 0x34) = 2;
122
123 *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8;
124 *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8;
125 *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8;
126 *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0;
127
128 *(volatile u8 *) (0xFED80D00 + 0x6c) = 1;
129 *(volatile u8 *) (0xFED80D00 + 0x6E) = 2;
130 *(volatile u8 *) (0xFED80D00 + 0x6f) = 2;
131
132 *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0;
133 *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8;
134 *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0;
135
136 *(volatile u8 *) (0xFED80D00 + 0xA6) = 2;
137 *(volatile u8 *) (0xFED80100 + 0xA6) = 0;
138
139 *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8;
140#endif
141 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
142#define IO_LOCAL_INT(type, intr, apicid, pin) \
143 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
Kyösti Mälkkib4261072014-07-22 10:24:20 +0300144 mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800145
146 /* PCI interrupts are level triggered, and are
147 * associated with a specific bus/device/function tuple.
148 */
149#define PCI_INT(bus, dev, int_sign, pin) \
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800151
152 /* Internal VGA */
153 PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
154 PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
155
156 /* SMBUS */
157 PCI_INT(0x0, 0x14, 0x0, 0x10);
158
159 /* HD Audio */
160 PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
161
162 /* USB */
163 PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
164 PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
165 PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
166 PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
167 PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
168 PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
169 PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
170
171 /* sata */
172 PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
173 PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
174
175 /* on board NIC & Slot PCIE. */
176
177 /* PCI slots */
Kyösti Mälkkic70eed12018-05-22 02:18:00 +0300178 struct device *dev = pcidev_on_root(0x14, 4);
Kyösti Mälkkicdfb4622014-07-22 15:24:15 +0300179 if (dev && dev->enabled) {
180 u8 bus_pci = dev->link_list->secondary;
181 /* PCI_SLOT 0. */
182 PCI_INT(bus_pci, 0x5, 0x0, 0x14);
183 PCI_INT(bus_pci, 0x5, 0x1, 0x15);
184 PCI_INT(bus_pci, 0x5, 0x2, 0x16);
185 PCI_INT(bus_pci, 0x5, 0x3, 0x17);
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800186
Kyösti Mälkkicdfb4622014-07-22 15:24:15 +0300187 /* PCI_SLOT 1. */
188 PCI_INT(bus_pci, 0x6, 0x0, 0x15);
189 PCI_INT(bus_pci, 0x6, 0x1, 0x16);
190 PCI_INT(bus_pci, 0x6, 0x2, 0x17);
191 PCI_INT(bus_pci, 0x6, 0x3, 0x14);
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800192
Kyösti Mälkkicdfb4622014-07-22 15:24:15 +0300193 /* PCI_SLOT 2. */
194 PCI_INT(bus_pci, 0x7, 0x0, 0x16);
195 PCI_INT(bus_pci, 0x7, 0x1, 0x17);
196 PCI_INT(bus_pci, 0x7, 0x2, 0x14);
197 PCI_INT(bus_pci, 0x7, 0x3, 0x15);
198 }
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800199
200 /* PCIe Lan*/
201 PCI_INT(0x0, 0x06, 0x0, 0x13);
202
203 /* FCH PCIe PortA */
204 PCI_INT(0x0, 0x15, 0x0, 0x10);
205 /* FCH PCIe PortB */
206 PCI_INT(0x0, 0x15, 0x1, 0x11);
207 /* FCH PCIe PortC */
208 PCI_INT(0x0, 0x15, 0x2, 0x12);
209 /* FCH PCIe PortD */
210 PCI_INT(0x0, 0x15, 0x3, 0x13);
211
212 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
213 IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
214 IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
215 /* There is no extension information... */
216
217 /* Compute the checksums */
218 return mptable_finalize(mc);
219}
220
221unsigned long write_smp_table(unsigned long addr)
222{
223 void *v;
224 v = smp_write_floating_table(addr, 0);
225 return (unsigned long)smp_write_config_table(v);
226}