blob: 65b86b88f7999f4c95f627de613dbd4af1b92c15 [file] [log] [blame]
Siyuan Wang80cf7d52013-07-09 17:42:43 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Siyuan Wang80cf7d52013-07-09 17:42:43 +080014 */
15
16/**
17 * @file
18 *
19 * AMD User options selection for a Brazos platform solution system
20 *
21 * This file is placed in the user's platform directory and contains the
22 * build option selections desired for that platform.
23 *
24 * For Information about this file, see @ref platforminstall.
25 *
Siyuan Wang80cf7d52013-07-09 17:42:43 +080026 */
27
Edward O'Callaghand5339ae2014-07-07 19:58:53 +100028#include <stdlib.h>
Elyes HAOUAS19f5ba82018-10-14 14:52:06 +020029#include <AGESA.h>
Siyuan Wang80cf7d52013-07-09 17:42:43 +080030
31#define INSTALL_FT3_SOCKET_SUPPORT TRUE
32#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
33
34#define INSTALL_G34_SOCKET_SUPPORT FALSE
35#define INSTALL_C32_SOCKET_SUPPORT FALSE
36#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
37#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
38#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
39#define INSTALL_FS1_SOCKET_SUPPORT FALSE
40#define INSTALL_FM1_SOCKET_SUPPORT FALSE
41#define INSTALL_FP2_SOCKET_SUPPORT FALSE
42#define INSTALL_FT1_SOCKET_SUPPORT FALSE
43#define INSTALL_AM3_SOCKET_SUPPORT FALSE
44#define INSTALL_FM2_SOCKET_SUPPORT FALSE
45
46
47#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
48 #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
49 #undef INSTALL_FT3_SOCKET_SUPPORT
50 #define INSTALL_FT3_SOCKET_SUPPORT FALSE
51 #endif
52#endif
53
54//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
55//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
56#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
57//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
58//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
59//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
60#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
61#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
62#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
63//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
64#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
65//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
66#define BLDOPT_REMOVE_SRAT FALSE //TRUE
67#define BLDOPT_REMOVE_SLIT FALSE //TRUE
68#define BLDOPT_REMOVE_WHEA FALSE //TRUE
69#define BLDOPT_REMOVE_CRAT TRUE
WANG Siyuan87bdd862013-11-18 10:34:06 +080070#define BLDOPT_REMOVE_CDIT TRUE
71#define BLDOPT_REMOVE_DMI TRUE
Siyuan Wang80cf7d52013-07-09 17:42:43 +080072//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
73//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
74//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
75//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
76//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
77//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
78
79//This element selects whether P-States should be forced to be independent,
80// as reported by the ACPI _PSD object. For single-link processors,
81// setting TRUE for OS to support this feature.
82
83//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
84
85#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
86#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
87/* Build configuration values here.
88 */
89#define BLDCFG_VRM_CURRENT_LIMIT 15000
90#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000
91#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000
92#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
93#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000
94#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
95#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
96#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
97#define BLDCFG_VRM_SLEW_RATE 10000
98#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE
99#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
100
101#define BLDCFG_PLAT_NUM_IO_APICS 3
102#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000
103#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
104#define BLDCFG_MEM_INIT_PSTATE 0
105#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the
106 // core for C-state entry requests. A value
107 // of 0 in this field specifies that the core
108 // does not trap any IO addresses for C-state entry.
109 // Values greater than 0xFFF8 results in undefined behavior.
110#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
111
112#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
113
114#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
115#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
116#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
117#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
118#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
119#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
120#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
121#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
122#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
123#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
124#define BLDCFG_MEMORY_POWER_DOWN TRUE
125#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
126#define BLDCFG_ONLINE_SPARE FALSE
127#define BLDCFG_BANK_SWIZZLE TRUE
128#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
129#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
130#define BLDCFG_DQS_TRAINING_CONTROL TRUE
131#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
132#define BLDCFG_USE_BURST_MODE FALSE
133#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
134#define BLDCFG_ENABLE_ECC_FEATURE TRUE
135#define BLDCFG_ECC_REDIRECTION FALSE
136#define BLDCFG_SCRUB_DRAM_RATE 0
137#define BLDCFG_SCRUB_L2_RATE 0
138#define BLDCFG_SCRUB_L3_RATE 0
139#define BLDCFG_SCRUB_IC_RATE 0
140#define BLDCFG_SCRUB_DC_RATE 0
141#define BLDCFG_ECC_SYNC_FLOOD TRUE
142#define BLDCFG_ECC_SYMBOL_SIZE 4
143#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul
144#define BLDCFG_1GB_ALIGN FALSE
145#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
146#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
147#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
148#define BLDCFG_IOMMU_SUPPORT FALSE
149#define OPTION_GFX_INIT_SVIEW FALSE
150//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife
151
152//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL
153#define BLDCFG_CFG_ABM_SUPPORT TRUE
154
Bruce Griffith17933e82013-07-10 01:26:26 -0600155#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800156//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
157//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
158//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
159
160#ifdef PCIEX_BASE_ADDRESS
161#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
162#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
163#endif
164
165#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
166#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
167#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
168
169/* Process the options...
170 * This file include MUST occur AFTER the user option selection settings
171 */
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800172/*
173 * Customized OEM build configurations for FCH component
174 */
175// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
176// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
177// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
178// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
179// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
180// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
181// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
182// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
183// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
184// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
185// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
186// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
187// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
188// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
189// #define BLDCFG_AZALIA_SSID 0x780D1022
190// #define BLDCFG_SMBUS_SSID 0x780B1022
191// #define BLDCFG_IDE_SSID 0x780C1022
192// #define BLDCFG_SATA_AHCI_SSID 0x78011022
193// #define BLDCFG_SATA_IDE_SSID 0x78001022
194// #define BLDCFG_SATA_RAID5_SSID 0x78031022
195// #define BLDCFG_SATA_RAID_SSID 0x78021022
196// #define BLDCFG_EHCI_SSID 0x78081022
197// #define BLDCFG_OHCI_SSID 0x78071022
198// #define BLDCFG_LPC_SSID 0x780E1022
199// #define BLDCFG_SD_SSID 0x78061022
200// #define BLDCFG_XHCI_SSID 0x78121022
201// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
202// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
203// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
204// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
205// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
206// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
207// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
208// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
209// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
210// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
211// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
212
213CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
214{
215 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
216 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
217 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
218 { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
219 { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
220 { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
221 { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
222 { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
223 { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
224 { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
225 { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
226 { CPU_LIST_TERMINAL }
227};
228
229#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList
230
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800231
232/* Include the files that instantiate the configuration definitions. */
233#include "cpuRegisters.h"
234#include "cpuFamRegisters.h"
235#include "cpuFamilyTranslation.h"
236#include "AdvancedApi.h"
237#include "heapManager.h"
238#include "CreateStruct.h"
239#include "cpuFeatures.h"
240#include "Table.h"
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800241#include "cpuEarlyInit.h"
242#include "cpuLateInit.h"
243#include "GnbInterface.h"
244
245 // This is the delivery package title, "BrazosPI"
246 // This string MUST be exactly 8 characters long
247#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
248
249 // This is the release version number of the AGESA component
250 // This string MUST be exactly 12 characters long
251#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
252
253/* MEMORY_BUS_SPEED */
254//#define DDR400_FREQUENCY 200 ///< DDR 400
255//#define DDR533_FREQUENCY 266 ///< DDR 533
256//#define DDR667_FREQUENCY 333 ///< DDR 667
257//#define DDR800_FREQUENCY 400 ///< DDR 800
258//#define DDR1066_FREQUENCY 533 ///< DDR 1066
259//#define DDR1333_FREQUENCY 667 ///< DDR 1333
260//#define DDR1600_FREQUENCY 800 ///< DDR 1600
261//#define DDR1866_FREQUENCY 933 ///< DDR 1866
262//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
263//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
264//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
265//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
266//
267///* QUANDRANK_TYPE*/
268//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
269//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
270//
271///* USER_MEMORY_TIMING_MODE */
272//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
273//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
274//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
275//
276///* POWER_DOWN_MODE */
277//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
278//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
279
280/*
281 * Agesa optional capabilities selection.
282 * Uncomment and mark FALSE those features you wish to include in the build.
283 * Comment out or mark TRUE those features you want to REMOVE from the build.
284 */
285
286#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
287#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
288#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
289#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
290#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
291#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
292#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
293#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
294#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
295#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
296#define DFLT_HPET_BASE_ADDRESS 0xFED00000
297#define DFLT_SMI_CMD_PORT 0xB0
298#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
299#define DFLT_GEC_BASE_ADDRESS 0xFED61000
300#define DFLT_AZALIA_SSID 0x780D1022
301#define DFLT_SMBUS_SSID 0x780B1022
302#define DFLT_IDE_SSID 0x780C1022
303#define DFLT_SATA_AHCI_SSID 0x78011022
304#define DFLT_SATA_IDE_SSID 0x78001022
305#define DFLT_SATA_RAID5_SSID 0x78031022
306#define DFLT_SATA_RAID_SSID 0x78021022
307#define DFLT_EHCI_SSID 0x78081022
308#define DFLT_OHCI_SSID 0x78071022
309#define DFLT_LPC_SSID 0x780E1022
310#define DFLT_SD_SSID 0x78061022
311#define DFLT_XHCI_SSID 0x78121022
312#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
313#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
314#define DFLT_FCH_GPP_LINK_CONFIG PortA4
315#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
316#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
317#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
318#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
319#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
320#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
321#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
322#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
323//#define BLDCFG_IR_PIN_CONTROL 0x33
324
325GPIO_CONTROL olivehill_gpio[] = {
326 {183, Function1, GpioIn | GpioOutEnB | PullUpB},
327 {-1}
328};
329//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0])
330
331// The following definitions specify the default values for various parameters in which there are
332// no clearly defined defaults to be used in the common file. The values below are based on product
333// and BKDG content, please consult the AGESA Memory team for consultation.
334#define DFLT_SCRUB_DRAM_RATE (0)
335#define DFLT_SCRUB_L2_RATE (0)
336#define DFLT_SCRUB_L3_RATE (0)
337#define DFLT_SCRUB_IC_RATE (0)
338#define DFLT_SCRUB_DC_RATE (0)
339#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
340#define DFLT_VRM_SLEW_RATE (5000)
341
Kyösti Mälkkic8e47422017-08-31 08:52:12 +0300342#include <PlatformInstall.h>