blob: d5de067814355702b353c97b18a7d868f75101d0 [file] [log] [blame]
Richard Spiegel6d61db02018-04-04 10:35:21 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2018 Advanced Micro Devices
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <soc/northbridge.h>
17#include <soc/pci_devs.h>
Patrick Rudolphe56189c2018-04-18 10:11:59 +020018#include <device/pci_ops.h>
Richard Spiegel6d61db02018-04-04 10:35:21 -070019
20uint32_t nb_ioapic_read(unsigned int index)
21{
22 pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
23 return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA);
24}
25
26void nb_ioapic_write(unsigned int index, uint32_t value)
27{
28 pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
29 pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value);
30}
31
32void *get_ap_entry_ptr(void)
33{
34 return (void *)nb_ioapic_read(AP_SCRATCH_REG);
35}
36
37void set_ap_entry_ptr(void *entry)
38{
39 nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry);
40}