Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 1 | chip soc/intel/apollolake |
| 2 | |
| 3 | device cpu_cluster 0 on |
| 4 | device lapic 0 on end |
| 5 | end |
| 6 | |
| 7 | register "pcie_rp0_clkreq_pin" = "0" # wifi/bt |
| 8 | # Disable unused clkreq of PCIe root ports |
| 9 | register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" |
| 10 | register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" |
| 11 | register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" |
| 12 | register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" |
| 13 | register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" |
| 14 | |
| 15 | # GPIO for PERST_0 |
| 16 | # If the Board has PERST_0 signal, assign the GPIO |
| 17 | # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF |
| 18 | register "prt0_gpio" = "GPIO_PRT0_UDEF" |
| 19 | |
| 20 | # EMMC TX DATA Delay 1 |
| 21 | # Refer to EDS-Vol2-22.3. |
| 22 | # [14:8] steps of delay for HS400, each 125ps. |
| 23 | # [6:0] steps of delay for SDR104/HS200, each 125ps. |
| 24 | register "emmc_tx_data_cntl1" = "0x0C16" |
| 25 | |
| 26 | # EMMC TX DATA Delay 2 |
| 27 | # Refer to EDS-Vol2-22.3. |
| 28 | # [30:24] steps of delay for SDR50, each 125ps. |
| 29 | # [22:16] steps of delay for DDR50, each 125ps. |
| 30 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 31 | # [6:0] steps of delay for SDR12, each 125ps. |
| 32 | register "emmc_tx_data_cntl2" = "0x28162828" |
| 33 | |
| 34 | # EMMC RX CMD/DATA Delay 1 |
| 35 | # Refer to EDS-Vol2-22.3. |
| 36 | # [30:24] steps of delay for SDR50, each 125ps. |
| 37 | # [22:16] steps of delay for DDR50, each 125ps. |
| 38 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 39 | # [6:0] steps of delay for SDR12, each 125ps. |
| 40 | register "emmc_rx_cmd_data_cntl1" = "0x00181717" |
| 41 | |
| 42 | # EMMC RX CMD/DATA Delay 2 |
| 43 | # Refer to EDS-Vol2-22.3. |
| 44 | # [17:16] stands for Rx Clock before Output Buffer |
| 45 | # [14:8] steps of delay for Auto Tuning Mode, each 125ps. |
| 46 | # [6:0] steps of delay for HS200, each 125ps. |
| 47 | register "emmc_rx_cmd_data_cntl2" = "0x10008" |
| 48 | |
| 49 | # Enable DPTF |
| 50 | register "dptf_enable" = "1" |
| 51 | |
| 52 | # Enable Audio Clock and Power gating |
| 53 | register "hdaudio_clk_gate_enable" = "1" |
| 54 | register "hdaudio_pwr_gate_enable" = "1" |
| 55 | register "hdaudio_bios_config_lockdown" = "1" |
| 56 | |
| 57 | # Enable lpss s0ix |
| 58 | register "lpss_s0ix_enable" = "1" |
| 59 | |
| 60 | # GPE configuration |
| 61 | # Note that GPE events called out in ASL code rely on this |
| 62 | # route, i.e., if this route changes then the affected GPE |
| 63 | # offset bits also need to be changed. This sets the PMC register |
| 64 | # GPE_CFG fields. |
| 65 | register "gpe0_dw1" = "PMC_GPE_N_31_0" |
| 66 | register "gpe0_dw2" = "PMC_GPE_N_63_32" |
| 67 | register "gpe0_dw3" = "PMC_GPE_SW_31_0" |
| 68 | |
| 69 | # Enable I2C2 bus early for TPM access |
| 70 | register "i2c[2].early_init" = "1" |
| 71 | |
| 72 | # Minimum SLP S3 assertion width 28ms. |
| 73 | register "slp_s3_assertion_width_usecs" = "28000" |
| 74 | |
| 75 | device domain 0 on |
| 76 | device pci 00.0 on end # - Host Bridge |
| 77 | device pci 00.1 on end # - DPTF |
| 78 | device pci 00.2 on end # - NPK |
| 79 | device pci 02.0 on end # - Gen |
| 80 | device pci 03.0 on end # - Iunit |
| 81 | device pci 0d.0 on end # - P2SB |
| 82 | device pci 0d.1 on end # - PMC |
| 83 | device pci 0d.2 on end # - SPI |
| 84 | device pci 0d.3 on end # - Shared SRAM |
| 85 | device pci 0e.0 on # - Audio |
| 86 | chip drivers/generic/max98357a |
Martin Roth | 2e6aeba | 2016-10-07 10:48:31 -0600 | [diff] [blame] | 87 | register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 88 | device generic 0 on end |
| 89 | end |
| 90 | end |
| 91 | device pci 11.0 off end # - ISH |
| 92 | device pci 12.0 off end # - SATA |
| 93 | device pci 13.0 off end # - Root Port 2 - PCIe-A 0 |
| 94 | device pci 13.1 off end # - Root Port 3 - PCIe-A 1 |
| 95 | device pci 13.2 off end # - Root Port 4 - PCIe-A 2 |
| 96 | device pci 13.3 off end # - Root Port 5 - PCIe-A 3 |
| 97 | device pci 14.0 on |
| 98 | chip drivers/intel/wifi |
| 99 | register "wake" = "GPE0_DW3_00" |
| 100 | device pci 00.0 on end |
| 101 | end |
| 102 | end # - Root Port 0 - PCIe-B 0 - Wifi |
| 103 | device pci 14.1 off end # - Root Port 1 - PCIe-B 1 |
| 104 | device pci 15.0 on end # - XHCI |
| 105 | device pci 15.1 off end # - XDCI |
| 106 | device pci 16.0 on # - I2C 0 |
| 107 | chip drivers/i2c/da7219 |
| 108 | register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" |
| 109 | register "btn_cfg" = "50" |
| 110 | register "mic_det_thr" = "500" |
| 111 | register "jack_ins_deb" = "20" |
| 112 | register "jack_det_rate" = ""32ms_64ms"" |
| 113 | register "jack_rem_deb" = "1" |
| 114 | register "a_d_btn_thr" = "0xa" |
| 115 | register "d_b_btn_thr" = "0x16" |
| 116 | register "b_c_btn_thr" = "0x21" |
| 117 | register "c_mic_btn_thr" = "0x3e" |
| 118 | register "btn_avg" = "4" |
| 119 | register "adc_1bit_rpt" = "1" |
| 120 | register "micbias_lvl" = "2600" |
| 121 | register "mic_amp_in_sel" = ""diff"" |
| 122 | device i2c 1a on end |
| 123 | end |
| 124 | end |
| 125 | device pci 16.1 on end # - I2C 1 |
| 126 | device pci 16.2 on |
| 127 | chip drivers/i2c/tpm |
| 128 | register "hid" = ""GOOG0005"" |
| 129 | register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" |
| 130 | device i2c 50 on end |
| 131 | end |
| 132 | end # - I2C 2 |
| 133 | device pci 16.3 on |
Furquan Shaikh | 8be4fdf | 2016-10-21 16:45:59 -0700 | [diff] [blame] | 134 | chip drivers/i2c/wacom_ts |
| 135 | register "generic" = "{ |
Janice Li | e19c80b | 2016-11-07 17:49:44 +0800 | [diff] [blame] | 136 | .hid = WCOMNTN2_HID, |
Furquan Shaikh | 8be4fdf | 2016-10-21 16:45:59 -0700 | [diff] [blame] | 137 | .cid = PNP0C50_CID, |
| 138 | .desc = WCOM_TS_DESC, |
| 139 | .irq = IRQ_EDGE_LOW(GPIO_21_IRQ), |
| 140 | .probed = 1, |
| 141 | }" |
| 142 | register "hid_desc_reg_offset" = "0x1" |
| 143 | device i2c 0xA on end |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 144 | end |
| 145 | end # - I2C 3 |
| 146 | device pci 17.0 on |
| 147 | chip drivers/i2c/generic |
| 148 | register "hid" = ""ELAN0000"" |
| 149 | register "desc" = ""ELAN Touchpad"" |
| 150 | register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" |
| 151 | register "wake" = "GPE0_DW1_15" |
| 152 | register "probed" = "1" |
| 153 | device i2c 15 on end |
| 154 | end |
| 155 | end # - I2C 4 |
| 156 | device pci 17.1 on end # - I2C 5 |
| 157 | device pci 17.2 on end # - I2C 6 |
| 158 | device pci 17.3 on end # - I2C 7 |
| 159 | device pci 18.0 on end # - UART 0 |
| 160 | device pci 18.1 on end # - UART 1 |
| 161 | device pci 18.2 on end # - UART 2 |
| 162 | device pci 18.3 on end # - UART 3 |
| 163 | device pci 19.0 on end # - SPI 0 |
| 164 | device pci 19.1 on end # - SPI 1 |
| 165 | device pci 19.2 on end # - SPI 2 |
| 166 | device pci 1a.0 on end # - PWM |
| 167 | device pci 1b.0 on end # - SDCARD |
| 168 | device pci 1c.0 on end # - eMMC |
| 169 | device pci 1e.0 off end # - SDIO |
| 170 | device pci 1f.0 on # - LPC |
| 171 | chip ec/google/chromeec |
| 172 | device pnp 0c09.0 on end |
| 173 | end |
| 174 | end |
| 175 | device pci 1f.1 on end # - SMBUS |
| 176 | end |
| 177 | end |