blob: 63e28aa4cad451c8da64843550141de730a2eb02 [file] [log] [blame]
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -05001#include <console/console.h>
2#include <device/pci.h>
3#include <string.h>
4#include <stdint.h>
5#include <arch/pirq_routing.h>
6
7#include <cpu/amd/amdk8_sysconf.h>
8
Paul Menzel95fe8fb2016-07-28 17:20:20 +02009static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
10 uint8_t devfn, uint8_t link0, uint16_t bitmap0,
11 uint8_t link1, uint16_t bitmap1, uint8_t link2,
12 uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
13 uint8_t slot, uint8_t rfu)
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050014{
15 pirq_info->bus = bus;
16 pirq_info->devfn = devfn;
Paul Menzel95fe8fb2016-07-28 17:20:20 +020017 pirq_info->irq[0].link = link0;
18 pirq_info->irq[0].bitmap = bitmap0;
19 pirq_info->irq[1].link = link1;
20 pirq_info->irq[1].bitmap = bitmap1;
21 pirq_info->irq[2].link = link2;
22 pirq_info->irq[2].bitmap = bitmap2;
23 pirq_info->irq[3].link = link3;
24 pirq_info->irq[3].bitmap = bitmap3;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050025 pirq_info->slot = slot;
26 pirq_info->rfu = rfu;
27}
28
Paul Menzel95fe8fb2016-07-28 17:20:20 +020029extern unsigned char bus_ck804_0; //1
30extern unsigned char bus_ck804_1; //2
31extern unsigned char bus_ck804_2; //3
32extern unsigned char bus_ck804_3; //4
33extern unsigned char bus_ck804_4; //5
34extern unsigned char bus_ck804_5; //6
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050035
36unsigned long write_pirq_routing_table(unsigned long addr)
37{
38
39 struct irq_routing_table *pirq;
40 struct irq_info *pirq_info;
41 unsigned slot_num;
42 uint8_t *v;
43 unsigned sbdn;
44
Paul Menzel95fe8fb2016-07-28 17:20:20 +020045 uint8_t sum = 0;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050046 int i;
47
Paul Menzel95fe8fb2016-07-28 17:20:20 +020048 get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050049 sbdn = sysconf.sbdn;
50
51 /* Align the table to be 16 byte aligned. */
52 addr += 15;
53 addr &= ~15;
54
Kyösti Mälkki9533d832014-06-26 05:30:54 +030055 /* This table must be between 0xf0000 & 0x100000 */
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050056 printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
57
58 pirq = (void *)(addr);
Paul Menzel95fe8fb2016-07-28 17:20:20 +020059 v = (uint8_t *) (addr);
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050060
61 pirq->signature = PIRQ_SIGNATURE;
Paul Menzel95fe8fb2016-07-28 17:20:20 +020062 pirq->version = PIRQ_VERSION;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050063
64 pirq->rtr_bus = bus_ck804_0;
Paul Menzel95fe8fb2016-07-28 17:20:20 +020065 pirq->rtr_devfn = ((sbdn + 9) << 3) | 0;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050066
67 pirq->exclusive_irqs = 0;
68
69 pirq->rtr_vendor = 0x10de;
70 pirq->rtr_device = 0x005c;
71
72 pirq->miniport_data = 0;
73
74 memset(pirq->rfu, 0, sizeof(pirq->rfu));
75
Paul Menzel95fe8fb2016-07-28 17:20:20 +020076 pirq_info = (void *)(&pirq->checksum + 1);
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050077 slot_num = 0;
78//pci bridge
Paul Menzel95fe8fb2016-07-28 17:20:20 +020079 write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 9) << 3) | 0, 0x1,
80 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
81 pirq_info++;
82 slot_num++;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050083
84#if 0
85//smbus
Paul Menzel95fe8fb2016-07-28 17:20:20 +020086 write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 1) << 3) | 0, 0x2,
87 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
88 pirq_info++;
89 slot_num++;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050090
91//usb
Paul Menzel95fe8fb2016-07-28 17:20:20 +020092 write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 2) << 3) | 0, 0x1,
93 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
94 pirq_info++;
95 slot_num++;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050096
97//audio
Paul Menzel95fe8fb2016-07-28 17:20:20 +020098 write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 4) << 3) | 0, 0x1,
99 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
100 pirq_info++;
101 slot_num++;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -0500102//sata
Paul Menzel95fe8fb2016-07-28 17:20:20 +0200103 write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 7) << 3) | 0, 0x1,
104 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
105 pirq_info++;
106 slot_num++;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -0500107//sata
Paul Menzel95fe8fb2016-07-28 17:20:20 +0200108 write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 8) << 3) | 0, 0x1,
109 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
110 pirq_info++;
111 slot_num++;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -0500112//nic
Paul Menzel95fe8fb2016-07-28 17:20:20 +0200113 write_pirq_info(pirq_info, bus_ck804_0, ((sbdn + 0xa) << 3) | 0, 0x1,
114 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
115 pirq_info++;
116 slot_num++;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -0500117
118//Slot1 PCIE x16
Paul Menzel95fe8fb2016-07-28 17:20:20 +0200119 write_pirq_info(pirq_info, bus_ck804_5, (0 << 3) | 0, 0x3, 0xdef8, 0x4,
120 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
121 pirq_info++;
122 slot_num++;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -0500123
124//firewire
Paul Menzel95fe8fb2016-07-28 17:20:20 +0200125 write_pirq_info(pirq_info, bus_ck804_1, (0x5 << 3) | 0, 0x3, 0xdef8, 0,
126 0, 0, 0, 0, 0, 0, 0);
127 pirq_info++;
128 slot_num++;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -0500129
130//Slot2 pci
Paul Menzel95fe8fb2016-07-28 17:20:20 +0200131 write_pirq_info(pirq_info, bus_ck804_1, (0x4 << 3) | 0, 0x1, 0xdef8,
132 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
133 pirq_info++;
134 slot_num++;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -0500135#endif
136
137 pirq->size = 32 + 16 * slot_num;
138
139 for (i = 0; i < pirq->size; i++)
140 sum += v[i];
141
142 sum = pirq->checksum - sum;
143
144 if (sum != pirq->checksum) {
145 pirq->checksum = sum;
146 }
147
148 printk(BIOS_INFO, "done.\n");
149
Paul Menzel95fe8fb2016-07-28 17:20:20 +0200150 return (unsigned long)pirq_info;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -0500151
152}