Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <string.h> |
| 21 | #include <vendorcode/google/chromeos/chromeos.h> |
| 22 | #include <arch/io.h> |
| 23 | #ifdef __PRE_RAM__ |
| 24 | #include <arch/romcc_io.h> |
| 25 | #else |
| 26 | #include <device/device.h> |
| 27 | #include <device/pci.h> |
| 28 | #endif |
| 29 | #include <southbridge/intel/bd82x6x/pch.h> |
| 30 | |
| 31 | #ifndef __PRE_RAM__ |
| 32 | #include <boot/coreboot_tables.h> |
| 33 | #include <arch/coreboot_tables.h> |
| 34 | |
| 35 | #define GPIO_COUNT 5 |
| 36 | #define ACTIVE_LOW 0 |
| 37 | #define ACTIVE_HIGH 1 |
| 38 | |
| 39 | void fill_lb_gpios(struct lb_gpios *gpios) |
| 40 | { |
| 41 | device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); |
| 42 | u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; |
| 43 | u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); |
| 44 | |
| 45 | if (!gpio_base) |
| 46 | return; |
| 47 | |
| 48 | #if 0 // Dev mode is hardcoded on, so we don't need to read these GPIOs. |
| 49 | u32 gp_lvl = inl(gpio_base + 0x0c); |
| 50 | #endif |
| 51 | u32 gp_lvl2 = inl(gpio_base + 0x38); |
| 52 | u32 gp_lvl3 = inl(gpio_base + 0x48); |
| 53 | |
| 54 | gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); |
| 55 | gpios->count = GPIO_COUNT; |
| 56 | |
| 57 | /* Write Protect: GPIO68 = CHP3_SPI_WP */ |
| 58 | gpios->gpios[0].port = 68; |
| 59 | gpios->gpios[0].polarity = ACTIVE_HIGH; |
| 60 | gpios->gpios[0].value = (gp_lvl3 >> (68-64)) & 1; |
| 61 | strncpy((char *)gpios->gpios[0].name,"write protect", |
| 62 | GPIO_MAX_NAME_LENGTH); |
| 63 | |
| 64 | /* Recovery: GPIO42 = CHP3_REC_MODE# */ |
| 65 | gpios->gpios[1].port = 42; |
| 66 | gpios->gpios[1].polarity = ACTIVE_LOW; |
| 67 | gpios->gpios[1].value = (gp_lvl2 >> (42-32)) & 1; |
| 68 | strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); |
| 69 | |
| 70 | /* Developer: GPIO17 = KBC3_DVP_MODE */ |
| 71 | gpios->gpios[2].port = 17; |
| 72 | gpios->gpios[2].polarity = ACTIVE_HIGH; |
| 73 | #if 0 // Dev mode is hardcoded on. |
| 74 | gpios->gpios[2].value = (gp_lvl >> 17) & 1; |
| 75 | #else |
| 76 | gpios->gpios[2].value = 1; |
| 77 | #endif |
| 78 | strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH); |
| 79 | |
| 80 | /* Hard code the lid switch GPIO to open. */ |
| 81 | gpios->gpios[3].port = 100; |
| 82 | gpios->gpios[3].polarity = ACTIVE_HIGH; |
| 83 | gpios->gpios[3].value = 1; |
| 84 | strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); |
| 85 | |
| 86 | /* Power Button */ |
| 87 | gpios->gpios[4].port = 101; |
| 88 | gpios->gpios[4].polarity = ACTIVE_LOW; |
| 89 | gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1; |
| 90 | strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); |
| 91 | } |
| 92 | #endif |
| 93 | |
| 94 | int get_developer_mode_switch(void) |
| 95 | { |
| 96 | #if 0 // Dev mode is hardcoded on. |
| 97 | device_t dev; |
| 98 | #ifdef __PRE_RAM__ |
| 99 | dev = PCI_DEV(0, 0x1f, 0); |
| 100 | #else |
| 101 | dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); |
| 102 | #endif |
| 103 | u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; |
| 104 | u32 gp_lvl = inl(gpio_base + 0x0c); |
| 105 | |
| 106 | /* Developer: GPIO17 = KBC3_DVP_MODE, active high */ |
| 107 | return (gp_lvl >> 17) & 1; |
| 108 | #else |
| 109 | return 1; |
| 110 | #endif |
| 111 | } |
| 112 | |
| 113 | int get_recovery_mode_switch(void) |
| 114 | { |
| 115 | device_t dev; |
| 116 | #ifdef __PRE_RAM__ |
| 117 | dev = PCI_DEV(0, 0x1f, 0); |
| 118 | #else |
| 119 | dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); |
| 120 | #endif |
| 121 | u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; |
| 122 | u32 gp_lvl2 = inl(gpio_base + 0x38); |
| 123 | |
| 124 | /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ |
| 125 | return !((gp_lvl2 >> (42-32)) & 1); |
| 126 | } |
| 127 | |