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Martin Roth58562402015-10-11 10:36:26 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Martin Roth58562402015-10-11 10:36:26 +020015 */
16
Elyes HAOUAS6d19a202018-11-22 11:15:29 +010017#include <arch/acpi.h>
Martin Roth58562402015-10-11 10:36:26 +020018DefinitionBlock(
19 "dsdt.aml",
20 "DSDT",
Elyes HAOUAS0cca6e22018-11-13 14:23:29 +010021 0x02, // DSDT revision: ACPI v2.0 and up
Elyes HAOUAS6d19a202018-11-22 11:15:29 +010022 OEM_ID,
23 ACPI_TABLE_CREATOR,
Martin Roth58562402015-10-11 10:36:26 +020024 0x20110725 // OEM revision
25)
26{
Martin Roth49fdf3f2015-11-26 15:58:12 -070027 // Include mainboard configuration
28 #include <acpi/mainboard.asl>
29
Martin Roth58562402015-10-11 10:36:26 +020030 // Include debug methods
31 #include <arch/x86/acpi/debug.asl>
32
33 // Some generic macros
34 #include "acpi/platform.asl"
35
36 // global NVS and variables
37 #include <southbridge/intel/fsp_rangeley/acpi/globalnvs.asl>
38
39 #include "acpi/thermal.asl"
40
Arthur Heymansaaced4a2018-11-28 13:53:15 +010041 #include <cpu/intel/common/acpi/cpu.asl>
Martin Roth58562402015-10-11 10:36:26 +020042
43 Scope (\_SB) {
44 Device (PCI0)
45 {
46 #include <northbridge/intel/fsp_rangeley/acpi/rangeley.asl>
47 #include <southbridge/intel/fsp_rangeley/acpi/soc.asl>
48 }
49 }
50
51 /* Chipset specific sleep states */
52 #include <southbridge/intel/fsp_rangeley/acpi/sleepstates.asl>
53}