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Martin Roth58562402015-10-11 10:36:26 +02001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Martin Roth58562402015-10-11 10:36:26 +020015
16if BOARD_INTEL_MOHONPEAK
17
Elyes HAOUASf0c5be22018-11-27 20:36:44 +010018config BOARD_SPECIFIC_OPTIONS
Martin Roth58562402015-10-11 10:36:26 +020019 def_bool y
Martin Roth58562402015-10-11 10:36:26 +020020 select NORTHBRIDGE_INTEL_FSP_RANGELEY
21 select SOUTHBRIDGE_INTEL_FSP_RANGELEY
22 select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB
23 select HAVE_ACPI_TABLES
24 select HAVE_OPTION_TABLE
Martin Roth58562402015-10-11 10:36:26 +020025 select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
26
27config MAINBOARD_DIR
28 string
29 default intel/mohonpeak
30
31config MAINBOARD_PART_NUMBER
32 string
33 default "Mohon Peak CRB"
34
35config MAX_CPUS
36 int
37 default 16
38
Martin Roth58562402015-10-11 10:36:26 +020039config FSP_FILE
40 string
41 default "../intel/fsp/rangeley/FvFsp.bin"
42
43config CBFS_SIZE
44 hex
45 default 0x00200000
46
47config ENABLE_FSP_FAST_BOOT
48 bool
49 depends on HAVE_FSP_BIN
50 default y
51
52config VIRTUAL_ROM_SIZE
53 hex
54 depends on ENABLE_FSP_FAST_BOOT
55 default 0x400000
56
57config FSP_PACKAGE_DEFAULT
58 bool "Configure defaults for the Intel FSP package"
59 default n
60
61config UART_FOR_CONSOLE
62 int
63 default 1
64 help
65 The Mohon Peak board uses COM2 (2f8) for the serial console.
66
Martin Roth9ed54f92015-12-06 12:14:42 -070067config PAYLOAD_CONFIGFILE
68 string
Lubomir Rintelc8832e12017-09-20 19:34:50 +020069 depends on PAYLOAD_SEABIOS
Martin Roth9ed54f92015-12-06 12:14:42 -070070 default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
71 help
Martin Roth58562402015-10-11 10:36:26 +020072 The Avoton/Rangeley chip does not allow devices to write into the 0xe000
73 segment. This means that USB/SATA devices will not work in SeaBIOS unless
74 we put the SeaBIOS buffer area down in the 0x9000 segment.
75
76endif # BOARD_INTEL_MOHONPEAK