blob: 3719154bdd015ba1ad9005e10321dacae5d4b0e7 [file] [log] [blame]
Martin Rothe6df0412014-07-28 14:22:32 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 Google Inc.
6 * Copyright (C) 2014 Sage Electronic Engineering, LLC.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Martin Rothe6df0412014-07-28 14:22:32 -060016 */
17
18#define INCLUDE_LPE 1
19#define INCLUDE_SCC 1
20#define INCLUDE_EHCI 1
21#define INCLUDE_XHCI 1
22#define INCLUDE_LPSS 1
23
24
Elyes HAOUAS6d19a202018-11-22 11:15:29 +010025#include <arch/acpi.h>
Martin Rothe6df0412014-07-28 14:22:32 -060026DefinitionBlock(
27 "dsdt.aml",
28 "DSDT",
Elyes HAOUAS0cca6e22018-11-13 14:23:29 +010029 0x02, // DSDT revision: ACPI v2.0 and up
Elyes HAOUAS6d19a202018-11-22 11:15:29 +010030 OEM_ID,
31 ACPI_TABLE_CREATOR,
Martin Rothe6df0412014-07-28 14:22:32 -060032 0x20110725 // OEM revision
33)
34{
35 // Some generic macros
36 #include <soc/intel/fsp_baytrail/acpi/platform.asl>
37
38 // global NVS and variables
39 #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
40
Arthur Heymansaaced4a2018-11-28 13:53:15 +010041 #include <cpu/intel/common/acpi/cpu.asl>
Martin Rothe6df0412014-07-28 14:22:32 -060042
43 Scope (\_SB) {
44 Device (PCI0)
45 {
46 #include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
47 }
48 }
49
50 /* Chipset specific sleep states */
51 #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl>
52
53 #include "acpi/mainboard.asl"
54}