blob: 1ef465aa199d0b5175f6d08e1694c4b1348b106b [file] [log] [blame]
Mariusz Szafranskifaf7a8e2017-08-02 18:51:47 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 - 2017 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef _MAINBOARD_GPIO_H
18#define _MAINBOARD_GPIO_H
19
Julien Viard de Galbert7ebb6b02018-03-01 16:03:31 +010020#include <soc/gpio_dnv.h>
Mariusz Szafranskifaf7a8e2017-08-02 18:51:47 +020021
22#ifndef __ACPI__
Julien Viard de Galbert7ebb6b02018-03-01 16:03:31 +010023const struct dnv_pad_config harcuvar_gpio_table[] = {
Mariusz Szafranskifaf7a8e2017-08-02 18:51:47 +020024 // GBE0_SDP0 (GPIO_14)
25 {NORTH_ALL_GBE0_SDP0,
26 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
27 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
28 // GBE1_SDP0 (GPIO_15)
29 {NORTH_ALL_GBE1_SDP0,
30 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
31 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
32 // GBE2_I2C_CLK (GPIO_16)
33 {NORTH_ALL_GBE0_SDP1,
34 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
35 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
36 // GBE2_I2C_DATA (GPIO_17)
37 {NORTH_ALL_GBE1_SDP1,
38 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
39 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
40 // GBE2_SDP0 (GPIO_18)
41 {NORTH_ALL_GBE0_SDP2,
42 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
43 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
44 // GBE3_SDP0 (GPIO_19)
45 {NORTH_ALL_GBE1_SDP2,
46 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
47 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
48 // GBE3_I2C_CLK (GPIO_20)
49 {NORTH_ALL_GBE0_SDP3,
50 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
51 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
52 // GBE3_I2C_DATA (GPIO_21)
53 {NORTH_ALL_GBE1_SDP3,
54 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
55 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
56 // GBE2_LED0 (GPIO_22)
57 {NORTH_ALL_GBE2_LED0,
58 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
59 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
60 // GBE2_LED1 (GPIO_23)
61 {NORTH_ALL_GBE2_LED1,
62 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
63 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
64 // GBE0_I2C_CLK (GPIO_24)
65 {NORTH_ALL_GBE0_I2C_CLK,
66 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
67 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
68 // GBE0_I2C_DATA (GPIO_25)
69 {NORTH_ALL_GBE0_I2C_DATA,
70 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
71 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
72 // GBE1_I2C_CLK (GPIO_26)
73 {NORTH_ALL_GBE1_I2C_CLK,
74 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
75 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
76 // GBE1_I2C_DATA (GPIO_27)
77 {NORTH_ALL_GBE1_I2C_DATA,
78 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
79 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
80 // NCSI_RXD0 (GPIO_28)
81 {NORTH_ALL_NCSI_RXD0,
82 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
83 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
84 // NCSI_CLK_IN (GPIO_29)
85 {NORTH_ALL_NCSI_CLK_IN,
86 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
87 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
88 // NCSI_RXD1 (GPIO_30)
89 {NORTH_ALL_NCSI_RXD1,
90 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
91 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
92 // NCSI_CRS_DV (GPIO_31)
93 {NORTH_ALL_NCSI_CRS_DV,
94 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
95 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
96 // NCSI_ARB_IN (GPIO_32)
97 {NORTH_ALL_NCSI_ARB_IN,
98 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
99 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
100 // NCSI_TX_EN (GPIO_33)
101 {NORTH_ALL_NCSI_TX_EN,
102 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
103 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
104 // NCSI_TXD0 (GPIO_34)
105 {NORTH_ALL_NCSI_TXD0,
106 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
107 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
108 // NCSI_TXD1 (GPIO_35)
109 {NORTH_ALL_NCSI_TXD1,
110 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
111 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
112 // NCSI_ARB_OUT (GPIO_36)
113 {NORTH_ALL_NCSI_ARB_OUT,
114 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
115 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
116 // GBE0_LED0 (GPIO_37)
117 {NORTH_ALL_GBE0_LED0,
118 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
119 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
120 // GBE0_LED1 (GPIO_38)
121 {NORTH_ALL_GBE0_LED1,
122 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
123 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
124 // GBE1_LED0 (GPIO_39)
125 {NORTH_ALL_GBE1_LED0,
126 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
127 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
128 // GBE1_LED1 (GPIO_40)
129 {NORTH_ALL_GBE1_LED1,
130 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
131 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
132 // ADR-COMPLETE (GPIO_0)
133 {NORTH_ALL_GPIO_0,
134 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
135 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
136 // PCIE_CLKREQ0_N (GPIO_41)
137 {NORTH_ALL_PCIE_CLKREQ0_N,
138 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
139 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
140 // PCIE_CLKREQ1_N (GPIO_42)
141 {NORTH_ALL_PCIE_CLKREQ1_N,
142 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
143 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
144 // PCIE_CLKREQ2_N (GPIO_43)
145 {NORTH_ALL_PCIE_CLKREQ2_N,
146 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
147 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
148 // PCIE_CLKREQ3_N (GPIO_44)
149 {NORTH_ALL_PCIE_CLKREQ3_N,
150 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
151 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
152 // FORCE_POWER (GPIO_45)
153 {NORTH_ALL_PCIE_CLKREQ4_N,
154 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
155 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
156 // GBE_MDC (GPIO_1)
157 {NORTH_ALL_GPIO_1,
158 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
159 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
160 // GBE_MDIO (GPIO_2)
161 {NORTH_ALL_GPIO_2,
162 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
163 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
164 // SVID_ALERT_N (GPIO_47)
165 {NORTH_ALL_SVID_ALERT_N,
166 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
167 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
168 // SVID_DATA (GPIO_48)
169 {NORTH_ALL_SVID_DATA,
170 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
171 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
172 // SVID_CLK (GPIO_49)
173 {NORTH_ALL_SVID_CLK,
174 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
175 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
176 // THERMTRIP_N (GPIO_50)
177 {NORTH_ALL_THERMTRIP_N,
178 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
179 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
180 // PROCHOT_N (GPIO_51)
181 {NORTH_ALL_PROCHOT_N,
182 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
183 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
184 // MEMHOT_N (GPIO_52)
185 {NORTH_ALL_MEMHOT_N,
186 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
187 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
188 // DFX_PORT_CLK0 (GPIO_53)
189 {SOUTH_DFX_DFX_PORT_CLK0,
190 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
191 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
192 // DFX_PORT_CLK1 (GPIO_54)
193 {SOUTH_DFX_DFX_PORT_CLK1,
194 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
195 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
196 // DFX_PORT0 (GPIO_55)
197 {SOUTH_DFX_DFX_PORT0,
198 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
199 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
200 // DFX_PORT1 (GPIO_56)
201 {SOUTH_DFX_DFX_PORT1,
202 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
203 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
204 // DFX_PORT2 (GPIO_57)
205 {SOUTH_DFX_DFX_PORT2,
206 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
207 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
208 // DFX_PORT3 (GPIO_58)
209 {SOUTH_DFX_DFX_PORT3,
210 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
211 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
212 // DFX_PORT4 (GPIO_59)
213 {SOUTH_DFX_DFX_PORT4,
214 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
215 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
216 // DFX_PORT5 (GPIO_60)
217 {SOUTH_DFX_DFX_PORT5,
218 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
219 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
220 // DFX_PORT6 (GPIO_61)
221 {SOUTH_DFX_DFX_PORT6,
222 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
223 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
224 // DFX_PORT7 (GPIO_62)
225 {SOUTH_DFX_DFX_PORT7,
226 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
227 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
228 // DFX_PORT8 (GPIO_63)
229 {SOUTH_DFX_DFX_PORT8,
230 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
231 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
232 // DFX_PORT9 (GPIO_134)
233 {SOUTH_DFX_DFX_PORT9,
234 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
235 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
236 // DFX_PORT10 (GPIO_135)
237 {SOUTH_DFX_DFX_PORT10,
238 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
239 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
240 // DFX_PORT11 (GPIO_136)
241 {SOUTH_DFX_DFX_PORT11,
242 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
243 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
244 // DFX_PORT12 (GPIO_137)
245 {SOUTH_DFX_DFX_PORT12,
246 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
247 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
248 // DFX_PORT13 (GPIO_138)
249 {SOUTH_DFX_DFX_PORT13,
250 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
251 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
252 // DFX_PORT14 (GPIO_139)
253 {SOUTH_DFX_DFX_PORT14,
254 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
255 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
256 // DFX_PORT15 (GPIO_140)
257 {SOUTH_DFX_DFX_PORT15,
258 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
259 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
260 // SPI_TPM_CS_N (GPIO_12)
261 {SOUTH_GROUP0_GPIO_12,
262 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
263 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
264 // SMB5_GBE_ALRT_N (GPIO_13)
265 {SOUTH_GROUP0_SMB5_GBE_ALRT_N,
266 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
267 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
268 // SMI (GPIO_98)
269 {SOUTH_GROUP0_PCIE_CLKREQ5_N,
270 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
271 GpioIntSmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
272 // NMI (GPIO_99)
273 {SOUTH_GROUP0_PCIE_CLKREQ6_N,
274 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
275 GpioIntNmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
276 // GBE3_LED0 (GPIO_100)
277 {SOUTH_GROUP0_PCIE_CLKREQ7_N,
278 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
279 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
280 // UART0_RXD (GPIO_101)
281 {SOUTH_GROUP0_UART0_RXD,
282 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
283 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
284 // UART0_TXD (GPIO_102)
285 {SOUTH_GROUP0_UART0_TXD,
286 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
287 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
288 // SMB5_GBE_CLK (GPIO_103)
289 {SOUTH_GROUP0_SMB5_GBE_CLK,
290 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
291 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
292 // SMB_GBE_DATA (GPIO_104)
293 {SOUTH_GROUP0_SMB5_GBE_DATA,
294 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
295 GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
296 // ERROR2_N (GPIO_105)
297 {SOUTH_GROUP0_ERROR2_N,
298 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
299 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
300 // ERROR1_N (GPIO_106)
301 {SOUTH_GROUP0_ERROR1_N,
302 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
303 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
304 // ERROR0_N (GPIO_107)
305 {SOUTH_GROUP0_ERROR0_N,
306 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
307 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
308 // IERR_N (CATERR_N) (GPIO_108)
309 {SOUTH_GROUP0_IERR_N,
310 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
311 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
312 // MCERR_N (GPIO_109)
313 {SOUTH_GROUP0_MCERR_N,
314 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
315 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
316 // SMB0_LEG_CLK (GPIO_110)
317 {SOUTH_GROUP0_SMB0_LEG_CLK,
318 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
319 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
320 // SMB0_LEG_DATA (GPIO_111)
321 {SOUTH_GROUP0_SMB0_LEG_DATA,
322 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
323 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
324 // SMB0_LEG_ALRT_N (GPIO_112)
325 {SOUTH_GROUP0_SMB0_LEG_ALRT_N,
326 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
327 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
328 // SMB1_HOST_DATA (GPIO_113)
329 {SOUTH_GROUP0_SMB1_HOST_DATA,
330 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
331 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
332 // SMB1_HOST_CLK (GPIO_114)
333 {SOUTH_GROUP0_SMB1_HOST_CLK,
334 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
335 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
336 // SMB2_PECI_DATA (GPIO_115)
337 {SOUTH_GROUP0_SMB2_PECI_DATA,
338 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
339 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
340 // SMB2_PECI_CLK (GPIO_116)
341 {SOUTH_GROUP0_SMB2_PECI_CLK,
342 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
343 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
344 // SMB4_CSME0_DATA (GPIO_117)
345 {SOUTH_GROUP0_SMB4_CSME0_DATA,
346 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
347 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
348 // SMB4_CSME0_CLK (GPIO_118)
349 {SOUTH_GROUP0_SMB4_CSME0_CLK,
350 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
351 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
352 // SMB4_CSME0_ALRT_N (GPIO_119)
353 {SOUTH_GROUP0_SMB4_CSME0_ALRT_N,
354 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
355 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
356 // USB_OC0_N (GPIO_120)
357 {SOUTH_GROUP0_USB_OC0_N,
358 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
359 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
360 // FLEX_CLK_SE0 (GPIO_121)
361 {SOUTH_GROUP0_FLEX_CLK_SE0,
362 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
363 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
364 // FLEX_CLK_SE1 (GPIO_122)
365 {SOUTH_GROUP0_FLEX_CLK_SE1,
366 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
367 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
368 // GBE3_LED1 (GPIO_4)
369 {SOUTH_GROUP0_GPIO_4,
370 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
371 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
372 // SMB3_IE0_CLK (GPIO_5)
373 {SOUTH_GROUP0_GPIO_5,
374 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
375 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
376 // SMB3_IE0_DATA (GPIO_6)
377 {SOUTH_GROUP0_GPIO_6,
378 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
379 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
380 // SMB3_IE0_ALERT_N (GPIO_7)
381 {SOUTH_GROUP0_GPIO_7,
382 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
383 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
384 // SATA0_LED (GPIO_90)
385 {SOUTH_GROUP0_SATA0_LED_N,
386 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
387 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
388 // SATA1_LED (GPIO_91)
389 {SOUTH_GROUP0_SATA1_LED_N,
390 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
391 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
392 // SATA_PDETECT0 (GPIO_92)
393 {SOUTH_GROUP0_SATA_PDETECT0,
394 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
395 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
396 // SATA_PDETECT1 (GPIO_93)
397 {SOUTH_GROUP0_SATA_PDETECT1,
398 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
399 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
400 // UART1_RTS (GPIO_94)
401 {SOUTH_GROUP0_SATA0_SDOUT,
402 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
403 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
404 // UART1_CTS (GPIO_95)
405 {SOUTH_GROUP0_SATA1_SDOUT,
406 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
407 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
408 // UART1_RXD (GPIO_96)
409 {SOUTH_GROUP0_UART1_RXD,
410 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
411 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
412 // UART1_TXD (GPIO_97)
413 {SOUTH_GROUP0_UART1_TXD,
414 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
415 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
416 // SMB6_CSME1_DATA (GPIO_8)
417 {SOUTH_GROUP0_GPIO_8,
418 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
419 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
420 // SMB6_CSME1_CLK (GPIO_9)
421 {SOUTH_GROUP0_GPIO_9,
422 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
423 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
424 // TCK (GPIO_141)
425 {SOUTH_GROUP0_TCK,
426 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
427 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
428 // TRST_N (GPIO_142)
429 {SOUTH_GROUP0_TRST_N,
430 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
431 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
432 // TMS (GPIO_143)
433 {SOUTH_GROUP0_TMS,
434 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
435 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
436 // TDI (GPIO_144)
437 {SOUTH_GROUP0_TDI,
438 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
439 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
440 // TDO (GPIO_145)
441 {SOUTH_GROUP0_TDO,
442 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
443 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
444 // CX_PRDY_N (GPIO_146)
445 {SOUTH_GROUP0_CX_PRDY_N,
446 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
447 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
448 // CX-PREQ_N (GPIO_147)
449 {SOUTH_GROUP0_CX_PREQ_N,
450 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
451 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
452 // ME_RECVR_HDR (GPIO_148)
453 {SOUTH_GROUP0_CTBTRIGINOUT,
454 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
455 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
456 // ADV_DBG_DFX_HDR (GPIO_149)
457 {SOUTH_GROUP0_CTBTRIGOUT,
458 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
459 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
460 // LAD2_SPI_IRQ_N (GPIO_150)
461 {SOUTH_GROUP0_DFX_SPARE2,
462 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
463 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
464 // SMB_PECI_ALRT_N (GPIO_151)
465 {SOUTH_GROUP0_DFX_SPARE3,
466 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
467 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
468 // SMB_CSME1_ALRT_N (GPIO_152)
469 {SOUTH_GROUP0_DFX_SPARE4,
470 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
471 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
472 // SUSPWRDNACK (GPIO_79)
473 {SOUTH_GROUP1_SUSPWRDNACK,
474 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
475 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
476 // PMU_SUSCLK (GPIO_80)
477 {SOUTH_GROUP1_PMU_SUSCLK,
478 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
479 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
480 // ADR_TRIGGER_N (GPIO_81)
481 {SOUTH_GROUP1_ADR_TRIGGER,
482 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
483 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
484 // PMU_SLP_S45_N (GPIO_82)
485 {SOUTH_GROUP1_PMU_SLP_S45_N,
486 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
487 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
488 // PMU_SLP_S3_N (GPIO_83)
489 {SOUTH_GROUP1_PMU_SLP_S3_N,
490 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
491 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
492 // PMU_WAKE_N (GPIO_84)
493 {SOUTH_GROUP1_PMU_WAKE_N,
494 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
495 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
496 // PMU_PWRBTN_N (GPIO_85)
497 {SOUTH_GROUP1_PMU_PWRBTN_N,
498 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
499 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
500 // PMU_RESETBUTTON_N (GPIO_86)
501 {SOUTH_GROUP1_PMU_RESETBUTTON_N,
502 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
503 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
504 // PMU_PLTRST_N (GPIO_87)
505 {SOUTH_GROUP1_PMU_PLTRST_N,
506 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
507 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
508 // PMU_SUS_STAT_N (GPIO_88)
509 {SOUTH_GROUP1_SUS_STAT_N,
510 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
511 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
512 // TDB_CIO_PLUG_EVENT (GPIO_89)
513 {SOUTH_GROUP1_SLP_S0IX_N,
514 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
515 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
516 // SPI_CS0_N (GPIO_72)
517 {SOUTH_GROUP1_SPI_CS0_N,
518 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
519 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
520 // SPI_CS1_N (GPIO_73)
521 {SOUTH_GROUP1_SPI_CS1_N,
522 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
523 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
524 // SPI_MOSI_IO0 (GPIO_74)
525 {SOUTH_GROUP1_SPI_MOSI_IO0,
526 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
527 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
528 // SPI_MISO_IO1 (GPIO_75)
529 {SOUTH_GROUP1_SPI_MISO_IO1,
530 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
531 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
532 // SPI_IO2 (GPIO_76)
533 {SOUTH_GROUP1_SPI_IO2,
534 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
535 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
536 // SPI_IO3 (GPIO_77)
537 {SOUTH_GROUP1_SPI_IO3,
538 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
539 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
540 // SPI_CLK (GPIO_78)
541 {SOUTH_GROUP1_SPI_CLK,
542 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
543 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
544 // LPC_AD0 (GPIO_64)
545 {SOUTH_GROUP1_ESPI_IO0,
546 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
547 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
548 // LPC_AD1 (GPIO_65)
549 {SOUTH_GROUP1_ESPI_IO1,
550 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
551 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
552 // LPC_AD2 (GPIO_66)
553 {SOUTH_GROUP1_ESPI_IO2,
554 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
555 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
556 // LPC_AD3 (GPIO_67)
557 {SOUTH_GROUP1_ESPI_IO3,
558 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
559 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
560 // LPC_FRAME_N (GPIO_68)
561 {SOUTH_GROUP1_ESPI_CS0_N,
562 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
563 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
564 // LPC_CLKOUT0 (GPIO_69)
565 {SOUTH_GROUP1_ESPI_CLK,
566 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
567 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
568 // LPC_CLKOUT1 (GPIO_70)
569 {SOUTH_GROUP1_ESPI_RST_N,
570 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
571 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
572 // LPC_CLKRUN_N (GPIO_71)
573 {SOUTH_GROUP1_ESPI_ALRT0_N,
574 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
575 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
576 // MFG_MODE_HDR (GPIO_10)
577 {SOUTH_GROUP1_GPIO_10,
578 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
579 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
580 // LPC_SERIRQ (GPIO_11)
581 {SOUTH_GROUP1_GPIO_11,
582 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
583 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
584 // EMMC-CMD (GPIO_123)
585 {SOUTH_GROUP1_EMMC_CMD,
586 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
587 GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
588 // EMMC-CSTROBE (GPIO_124)
589 {SOUTH_GROUP1_EMMC_STROBE,
590 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
591 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
592 // EMMC-CLK (GPIO_125)
593 {SOUTH_GROUP1_EMMC_CLK,
594 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
595 GpioIntDefault, GpioResetDefault, GpioTermWpd20K, GpioLockDefault} },
596 // EMMC-D0 (GPIO_126)
597 {SOUTH_GROUP1_EMMC_D0,
598 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
599 GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
600 // EMMC-D1 (GPIO_127)
601 {SOUTH_GROUP1_EMMC_D1,
602 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
603 GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
604 // EMMC-D2 (GPIO_128)
605 {SOUTH_GROUP1_EMMC_D2,
606 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
607 GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
608 // EMMC-D3 (GPIO_129)
609 {SOUTH_GROUP1_EMMC_D3,
610 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
611 GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
612 // EMMC-D4 (GPIO_130)
613 {SOUTH_GROUP1_EMMC_D4,
614 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
615 GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
616 // EMMC-D5 (GPIO_131)
617 {SOUTH_GROUP1_EMMC_D5,
618 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
619 GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
620 // EMMC-D6 (GPIO_132)
621 {SOUTH_GROUP1_EMMC_D6,
622 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
623 GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
624 // EMMC-D7 (GPIO_133)
625 {SOUTH_GROUP1_EMMC_D7,
626 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
627 GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
628 // IE_ROM GPIO (GPIO_3)
629 {SOUTH_GROUP1_GPIO_3,
630 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
631 GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
632};
633#endif
634
635#endif /* _MAINBOARD_GPIO_H */