blob: 9d43b11e0725142c054493635308795015fe1902 [file] [log] [blame]
Mariusz Szafranskifaf7a8e2017-08-02 18:51:47 +02001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2014 - 2017 Intel Corporation.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15
16if BOARD_INTEL_HARCUVAR
17
18config BOARD_SPECIFIC_OPTIONS
19 def_bool y
20 select SOC_INTEL_DENVERTON_NS
21 select BOARD_ROMSIZE_KB_16384
22 select HAVE_ACPI_TABLES
23
24config MAINBOARD_DIR
25 string
26 default intel/harcuvar
27
28config MAINBOARD_PART_NUMBER
29 string
30 default "Harcuvar CRB"
31
32config MAINBOARD_VENDOR
33 string
34 default "Intel"
35
36config ENABLE_FSP_MEMORY_DOWN
37 bool "Enable Memory Down"
38 default n
39 help
40 Select this option to enable Memory Down function.
41
42config SPD_LOC
43 depends on ENABLE_FSP_MEMORY_DOWN
44 hex "SPD binary location in cbfs"
45 default 0xfffdf000
46 help
47 Location of SPD binary for memory down function.
48
49endif # BOARD_INTEL_HARCUVAR