blob: 1173ee4745730386eea547d8471d0122746be3df [file] [log] [blame]
Hannah Williamsd59f62b2017-05-05 16:39:21 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2017 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <baseboard/variants.h>
17#include <gpio.h>
18#include <soc/meminit.h>
19#include <variant/gpio.h>
20
21const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
22 /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
23 .phys[LP4_PHYS_CH0A] = {
24 /* DQA[0:7] pins of LPDDR4 module. */
25 .dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 },
26 /* DQA[8:15] pins of LPDDR4 module. */
27 .dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 },
28 /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
29 .dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 },
30 /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
31 .dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 },
32 },
33 .phys[LP4_PHYS_CH0B] = {
34 /* DQA[0:7] pins of LPDDR4 module. */
35 .dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 },
36 /* DQA[8:15] pins of LPDDR4 module. */
37 .dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 },
38 /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
39 .dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 },
40 /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
41 .dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 },
42 },
43 .phys[LP4_PHYS_CH1A] = {
44 /* DQA[0:7] pins of LPDDR4 module. */
45 .dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 },
46 /* DQA[8:15] pins of LPDDR4 module. */
47 .dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 },
48 /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
49 .dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 },
50 /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
51 .dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 },
52 },
53 .phys[LP4_PHYS_CH1B] = {
54 /* DQA[0:7] pins of LPDDR4 module. */
55 .dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 },
56 /* DQA[8:15] pins of LPDDR4 module. */
57 .dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 },
58 /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
59 .dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 },
60 /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
61 .dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 },
62 },
63};
64
65static const struct lpddr4_sku skus[] = {
66 /*
67 * K4F6E304HB-MGCJ - both logical channels While the parts
68 * are listed at 16Gb there are 2 ranks per channel so indicate
69 * the density as 8Gb per rank.
70 */
71 [0] = {
72 .speed = LP4_SPEED_2400,
73 .ch0_rank_density = LP4_8Gb_DENSITY,
74 .ch1_rank_density = LP4_8Gb_DENSITY,
75 .ch0_dual_rank = 1,
76 .ch1_dual_rank = 1,
77 .part_num = "K4F6E304HB-MGCJ",
78 },
79 /* K4F8E304HB-MGCJ - both logical channels */
80 [1] = {
81 .speed = LP4_SPEED_2400,
82 .ch0_rank_density = LP4_8Gb_DENSITY,
83 .ch1_rank_density = LP4_8Gb_DENSITY,
84 .part_num = "K4F8E304HB-MGCJ",
85 },
86 /*
87 * MT53B512M32D2NP-062WT:C - both logical channels. While the parts
88 * are listed at 16Gb there are 2 ranks per channel so indicate
89 * the density as 8Gb per rank.
90 */
91 [2] = {
92 .speed = LP4_SPEED_2400,
93 .ch0_rank_density = LP4_8Gb_DENSITY,
94 .ch1_rank_density = LP4_8Gb_DENSITY,
95 .ch0_dual_rank = 1,
96 .ch1_dual_rank = 1,
97 .part_num = "MT53B512M32D2NP",
98 .disable_periodic_retraining = 1,
99 },
100 /* MT53B256M32D1NP-062 WT:C - both logical channels */
101 [3] = {
102 .speed = LP4_SPEED_2400,
103 .ch0_rank_density = LP4_8Gb_DENSITY,
104 .ch1_rank_density = LP4_8Gb_DENSITY,
105 .part_num = "MT53B256M32D1NP",
106 .disable_periodic_retraining = 1,
107 },
108 /*
109 * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
110 * are listed at 16Gb there are 2 ranks per channel so indicate the
111 * density as 8Gb per rank.
112 */
113 [4] = {
114 .speed = LP4_SPEED_2400,
115 .ch0_rank_density = LP4_8Gb_DENSITY,
116 .ch1_rank_density = LP4_8Gb_DENSITY,
117 .ch0_dual_rank = 1,
118 .ch1_dual_rank = 1,
119 .part_num = "H9HCNNNBPUMLHR",
120 },
121 /* H9HCNNN8KUMLHR-NLE - both logical channels */
122 [5] = {
123 .speed = LP4_SPEED_2400,
124 .ch0_rank_density = LP4_8Gb_DENSITY,
125 .ch1_rank_density = LP4_8Gb_DENSITY,
126 .part_num = "H9HCNNN8KUMLHR",
127 },
128};
129
130static const struct lpddr4_cfg lp4cfg = {
131 .skus = skus,
132 .num_skus = ARRAY_SIZE(skus),
133 .swizzle_config = &baseboard_lpddr4_swizzle,
134};
135
Aaron Durbin64031672018-04-21 14:45:32 -0600136const struct lpddr4_cfg * __weak variant_lpddr4_config(void)
Hannah Williamsd59f62b2017-05-05 16:39:21 -0700137{
138 return &lp4cfg;
139}
140
Aaron Durbin64031672018-04-21 14:45:32 -0600141size_t __weak variant_memory_sku(void)
Hannah Williamsd59f62b2017-05-05 16:39:21 -0700142{
143 return 0;
144}