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Hannah Williamsd59f62b2017-05-05 16:39:21 -07001chip soc/intel/apollolake
2
3 device cpu_cluster 0 on
4 device lapic 0 on end
5 end
6
Furquan Shaikh6d5e10c2018-03-14 19:57:16 -07007 register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
Hannah Williamsd59f62b2017-05-05 16:39:21 -07008 # Disable unused clkreq of PCIe root ports
Furquan Shaikh6d5e10c2018-03-14 19:57:16 -07009 register "pcie_rp_clkreq_pin[1]" = "3" # wifi/bt
10 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
11 register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
Roy Mingi Parka6ab9af2018-03-01 11:09:58 -080012 register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
Furquan Shaikh6d5e10c2018-03-14 19:57:16 -070013 register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
Hannah Williamsd59f62b2017-05-05 16:39:21 -070014
15 # GPIO for PERST_0
16 # If the Board has PERST_0 signal, assign the GPIO
17 # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
Roy Mingi Parka6ab9af2018-03-01 11:09:58 -080018 register "prt0_gpio" = "GPIO_163"
Hannah Williamsd59f62b2017-05-05 16:39:21 -070019
20 # GPIO for SD card detect
21 register "sdcard_cd_gpio" = "GPIO_186"
22
23 # EMMC TX DATA Delay 1
24 # Refer to EDS-Vol2-22.3.
25 # [14:8] steps of delay for HS400, each 125ps.
26 # [6:0] steps of delay for SDR104/HS200, each 125ps.
27 register "emmc_tx_data_cntl1" = "0x0C3A"
28
29 # EMMC TX DATA Delay 2
30 # Refer to EDS-Vol2-22.3.
31 # [30:24] steps of delay for SDR50, each 125ps.
32 # [22:16] steps of delay for DDR50, each 125ps.
33 # [14:8] steps of delay for SDR25/HS50, each 125ps.
34 # [6:0] steps of delay for SDR12, each 125ps.
35 register "emmc_tx_data_cntl2" = "0x28272929"
36
37 # EMMC RX CMD/DATA Delay 1
38 # Refer to EDS-Vol2-22.3.
39 # [30:24] steps of delay for SDR50, each 125ps.
40 # [22:16] steps of delay for DDR50, each 125ps.
41 # [14:8] steps of delay for SDR25/HS50, each 125ps.
42 # [6:0] steps of delay for SDR12, each 125ps.
43 register "emmc_rx_cmd_data_cntl1" = "0x003B263B"
44
45 # EMMC RX CMD/DATA Delay 2
46 # Refer to EDS-Vol2-22.3.
47 # [17:16] stands for Rx Clock before Output Buffer
48 # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
49 # [6:0] steps of delay for HS200, each 125ps.
50 register "emmc_rx_cmd_data_cntl2" = "0x10008"
51
52 register "emmc_rx_strobe_cntl" = "0x0a0a"
53 register "emmc_tx_cmd_cntl" = "0x1305"
54
55 # Enable DPTF
56 register "dptf_enable" = "1"
57
Cole Nelson735779c2017-05-18 15:39:22 -070058 # PL1 override: 7.5W setting gives a run-time 6W actual
59 register "tdp_pl1_override_mw" = "7500"
Hannah Williamsd59f62b2017-05-05 16:39:21 -070060 # Set RAPL PL2 to 15W.
61 register "tdp_pl2_override_mw" = "15000"
62
63 # Enable Audio Clock and Power gating
64 register "hdaudio_clk_gate_enable" = "1"
65 register "hdaudio_pwr_gate_enable" = "1"
66 register "hdaudio_bios_config_lockdown" = "1"
67
68 # Enable lpss s0ix
69 register "lpss_s0ix_enable" = "1"
70
71 # GPE configuration
72 # Note that GPE events called out in ASL code rely on this
73 # route, i.e., if this route changes then the affected GPE
74 # offset bits also need to be changed. This sets the PMC register
75 # GPE_CFG fields.
76 #PMC_GPE_NW_63_32 - 03
77 #PMC_GPE_N_95_64 - 08
78 #PMC_GPE_NW_31_0 - 02
79 register "gpe0_dw1" = "PMC_GPE_NW_63_32"
80 register "gpe0_dw2" = "PMC_GPE_N_95_64"
81 register "gpe0_dw3" = "PMC_GPE_NW_31_0"
82
Subrata Banikc4986eb2018-05-09 14:55:09 +053083 # Intel Common SoC Config
84 #+-------------------+---------------------------+
85 #| Field | Value |
86 #+-------------------+---------------------------+
87 #| I2C0 | Audio |
88 #+-------------------+---------------------------+
89 register "common_soc_config" = "{
90 .i2c[0] = {
91 .speed = I2C_SPEED_FAST,
92 .rise_time_ns = 104,
93 .fall_time_ns = 52,
94 },
Hannah Williams7427abc2017-06-20 14:31:44 -070095 }"
Hannah Williamsd59f62b2017-05-05 16:39:21 -070096
97 # Minimum SLP S3 assertion width 28ms.
98 register "slp_s3_assertion_width_usecs" = "28000"
99
Pratik Prajapati73f073d2017-08-29 15:42:27 -0700100 register "sgx_enable" = "1"
101
102 # PRMRR size options
103 # 0x02000000 - 32MiB
104 # 0x04000000 - 64MiB
105 # 0x08000000 - 128MiB
106 register "PrmrrSize" = "128 * MiB"
107
Shaunak Sahacf1ba952018-03-21 07:39:40 -0700108 register "pnp_settings" = "PNP_PERF_POWER"
109
Hannah Williamsd59f62b2017-05-05 16:39:21 -0700110 device domain 0 on
111 device pci 00.0 on end # - Host Bridge
112 device pci 00.1 on end # - DPTF
113 device pci 00.2 on end # - NPK
114 device pci 02.0 on end # - Gen
115 device pci 03.0 on end # - Iunit
116 device pci 0c.0 on end # - CNVi
117 device pci 0d.0 on end # - P2SB
118 device pci 0d.1 on end # - PMC
119 device pci 0d.2 on end # - SPI
120 device pci 0d.3 on end # - Shared SRAM
Hannah Williams7427abc2017-06-20 14:31:44 -0700121 device pci 0e.0 on # - Audio
122 chip drivers/generic/max98357a
123 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_160)"
124 register "sdmode_delay" = "5"
125 device generic 0 on end
126 end
127 end
Hannah Williamsd59f62b2017-05-05 16:39:21 -0700128 device pci 0f.0 on end # - Heci1
129 device pci 0f.1 on end # - Heci2
130 device pci 0f.2 on end # - Heci3
131 device pci 11.0 off end # - ISH
132 device pci 12.0 on end # - SATA
133 device pci 13.0 off end # - PCIe-A 0 Slot 1
134 device pci 13.1 off end # - PCIe-A 1
Roy Mingi Parka6ab9af2018-03-01 11:09:58 -0800135 device pci 13.2 off end # - PCIe-A 2 Onboard Lan
Hannah Williamsd59f62b2017-05-05 16:39:21 -0700136 device pci 13.3 off end # - PCIe-A 3
Roy Mingi Parka6ab9af2018-03-01 11:09:58 -0800137 device pci 14.0 off end # - PCIe-B 0 Slot2
Hannah Williamsd59f62b2017-05-05 16:39:21 -0700138 device pci 14.1 on end # - PCIe-B 1 Onboard M2 Slot(Wifi/BT)
139 device pci 15.0 on end # - XHCI
140 device pci 15.1 off end # - XDCI
Hannah Williams7427abc2017-06-20 14:31:44 -0700141 device pci 16.0 on # - I2C 0
142 chip drivers/i2c/da7219
143 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_20_IRQ)"
144 register "btn_cfg" = "50"
145 register "mic_det_thr" = "500"
146 register "jack_ins_deb" = "20"
147 register "jack_det_rate" = ""32ms_64ms""
148 register "jack_rem_deb" = "1"
149 register "a_d_btn_thr" = "0xa"
150 register "d_b_btn_thr" = "0x16"
151 register "b_c_btn_thr" = "0x21"
152 register "c_mic_btn_thr" = "0x3e"
153 register "btn_avg" = "4"
154 register "adc_1bit_rpt" = "1"
155 register "micbias_lvl" = "2600"
156 register "mic_amp_in_sel" = ""diff""
157 device i2c 1a on end
158 end
159 end
Hannah Williamsd59f62b2017-05-05 16:39:21 -0700160 device pci 16.1 off end # - I2C 1
161 device pci 16.2 off end # - I2C 2
162 device pci 16.3 off end # - I2C 3
Shaunak Sahaced08642017-11-29 00:19:54 -0800163 device pci 17.0 on
164 chip drivers/i2c/hid
165 register "generic.hid" = ""ALPS0001""
166 register "generic.desc" = ""Touchpad""
167 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
168 register "hid_desc_reg_offset" = "0x1"
169 device i2c 2C on end
170 end
171 end # I2C 4
Hannah Williamsd59f62b2017-05-05 16:39:21 -0700172 device pci 17.1 off end # - I2C 5
173 device pci 17.2 off end # - I2C 6
174 device pci 17.3 on end # - I2C 7
175 device pci 18.0 on end # - UART 0
176 device pci 18.1 off end # - UART 1
177 device pci 18.2 on end # - UART 2
178 device pci 18.3 off end # - UART 3
179 device pci 19.0 on end # - SPI 0
180 device pci 19.1 on end # - SPI 1
181 device pci 19.2 on end # - SPI 2
182 device pci 1a.0 on end # - PWM
183 device pci 1b.0 on end # - SDCARD
184 device pci 1c.0 on end # - eMMC
185 device pci 1e.0 off end # - SDIO
186 device pci 1f.0 on # - LPC
187 chip drivers/pc80/tpm
188 register "irq_polarity" = "2"
189 device pnp 0c31.0 on
190 irq 0x70 = 10
191 end
192 end
193 chip ec/google/chromeec
194 device pnp 0c09.0 on end
195 end
196 end
197 device pci 1f.1 on end # - SMBUS
198 end
199end