blob: ddb805adbec57e285c6e192218ac6a1bfb84a2ae [file] [log] [blame]
Hannah Williamsd59f62b2017-05-05 16:39:21 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2017 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <arch/acpi.h>
17#include <baseboard/variants.h>
18#include <boardid.h>
19#include <console/console.h>
20#include <device/device.h>
21#include <ec/ec.h>
22#include <nhlt.h>
23#include <soc/gpio.h>
24#include <soc/nhlt.h>
25#include <vendorcode/google/chromeos/chromeos.h>
26#include <variant/ec.h>
27#include <variant/gpio.h>
28
29static void mainboard_init(void *chip_info)
30{
31 int boardid;
32 const struct pad_config *pads;
33 size_t num;
34
35 boardid = board_id();
36 printk(BIOS_INFO, "Board ID: %d\n", boardid);
37
38 pads = variant_gpio_table(&num);
39 gpio_configure_pads(pads, num);
40
41 mainboard_ec_init();
42}
43
44static unsigned long mainboard_write_acpi_tables(
Elyes HAOUAS5eec2292018-05-16 11:36:28 +020045 struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
Hannah Williamsd59f62b2017-05-05 16:39:21 -070046{
47 uintptr_t start_addr;
48 uintptr_t end_addr;
49 struct nhlt *nhlt;
50
51 start_addr = current;
52
53 nhlt = nhlt_init();
54
55 if (nhlt == NULL)
56 return start_addr;
57
58 variant_nhlt_init(nhlt);
59
60 end_addr = nhlt_soc_serialize(nhlt, start_addr);
61
62 if (end_addr != start_addr)
63 acpi_add_table(rsdp, (void *)start_addr);
64
65 return end_addr;
66}
67
Elyes HAOUAS5eec2292018-05-16 11:36:28 +020068static void mainboard_enable(struct device *dev)
Hannah Williamsd59f62b2017-05-05 16:39:21 -070069{
70 dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
71 dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
72}
73
74struct chip_operations mainboard_ops = {
75 .init = mainboard_init,
76 .enable_dev = mainboard_enable,
77};