blob: 44b7824224c8a42fe81b67e6b6d655b518301e74 [file] [log] [blame]
Hannah Williamsd59f62b2017-05-05 16:39:21 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2017 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <arch/acpi.h>
17#include <arch/io.h>
18#include <console/console.h>
19#include <ec/ec.h>
20#include <ec/google/chromeec/ec.h>
Ravi Sarawadiefa606b2017-08-04 16:26:09 -070021#include <intelblocks/lpc_lib.h>
Hannah Williamsd59f62b2017-05-05 16:39:21 -070022#include <variant/ec.h>
23
24static void ramstage_ec_init(void)
25{
Furquan Shaikh2749c522017-10-04 14:01:41 -070026 const struct google_chromeec_event_info info = {
27 .log_events = MAINBOARD_EC_LOG_EVENTS,
28 .sci_events = MAINBOARD_EC_SCI_EVENTS,
29 .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
30 .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
Shamile Khanb0bea2b2018-01-26 09:16:35 -080031 .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
Furquan Shaikh2749c522017-10-04 14:01:41 -070032 };
33
Hannah Williamsd59f62b2017-05-05 16:39:21 -070034 printk(BIOS_ERR, "mainboard: EC init\n");
35
Furquan Shaikh2749c522017-10-04 14:01:41 -070036 google_chromeec_events_init(&info, acpi_is_wakeup_s3());
Hannah Williamsd59f62b2017-05-05 16:39:21 -070037}
38
39static void bootblock_ec_init(void)
40{
41 uint16_t ec_ioport_base;
42 size_t ec_ioport_size;
Ravi Sarawadiefa606b2017-08-04 16:26:09 -070043
Hannah Williamsd59f62b2017-05-05 16:39:21 -070044 /*
45 * Set up LPC decoding for the ChromeEC I/O port ranges:
46 * - Ports 62/66, 60/64, and 200->208
47 * - ChromeEC specific communication I/O ports.
48 */
Ravi Sarawadiefa606b2017-08-04 16:26:09 -070049 lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
50 | LPC_IOE_LGE_200);
Hannah Williamsd59f62b2017-05-05 16:39:21 -070051 google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
52 lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
53}
54
55void mainboard_ec_init(void)
56{
Julius Wernercd49cce2019-03-05 16:53:33 -080057 if (CONFIG(EC_GOOGLE_CHROMEEC)) {
Hannah Williamsd59f62b2017-05-05 16:39:21 -070058 if (ENV_RAMSTAGE)
59 ramstage_ec_init();
60 else if (ENV_BOOTBLOCK)
61 bootblock_ec_init();
Ravi Sarawadiefa606b2017-08-04 16:26:09 -070062 } else if (ENV_BOOTBLOCK) {
63 /*
64 * Set up LPC decoding for the ChromeEC I/O port ranges:
65 * - Ports 62/66, 60/64, and 200->208
66 * - ChromeEC specific communication I/O ports.
67 */
68 lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
69 | LPC_IOE_LGE_200);
70 }
Hannah Williamsd59f62b2017-05-05 16:39:21 -070071
Julius Wernercd49cce2019-03-05 16:53:33 -080072 if (CONFIG(GLK_INTEL_EC)) {
Hannah Williamsd59f62b2017-05-05 16:39:21 -070073 printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa,0x66)\n");
74 outb(0xaa, 0x66);
Srinidhi Kaushik9e0dd012017-10-30 14:45:40 -070075 printk(BIOS_INFO, "Hack to turn on the CPU fan\n");
76 outb(0x81, 0x66);
77 outb(0x44, 0x62);
78 outb(0x32, 0x62);
79 /* Need delay here, hence second outb */
80 outb(0x32, 0x62);
81 outb(0x1a, 0x66);
Hannah Williamsd59f62b2017-05-05 16:39:21 -070082 }
83}