blob: 4edd4a0ab48d01a4f5c51fce640e4a8accdea49a [file] [log] [blame]
Hannah Williamsd59f62b2017-05-05 16:39:21 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2017 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <baseboard/variants.h>
17#include <boot/coreboot_tables.h>
18#include <ec/google/chromeec/ec.h>
19#include <gpio.h>
20#include <vendorcode/google/chromeos/chromeos.h>
21#include <soc/gpio.h>
22#include <variant/gpio.h>
23
24void fill_lb_gpios(struct lb_gpios *gpios)
25{
26 struct lb_gpio chromeos_gpios[] = {
27 {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
Hannah Williamsd59f62b2017-05-05 16:39:21 -070028 {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
29 {-1, ACTIVE_HIGH, 0, "power"},
30 {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
Shaunak Sahaf08ed7d2017-10-26 16:58:05 -070031 {-1, ACTIVE_HIGH, 0, "EC in RW"},
Hannah Williamsd59f62b2017-05-05 16:39:21 -070032 };
33 lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
34}
35
Hannah Williamsd59f62b2017-05-05 16:39:21 -070036int get_write_protect_state(void)
37{
Shaunak Sahaf08ed7d2017-10-26 16:58:05 -070038 return 0;
Hannah Williamsd59f62b2017-05-05 16:39:21 -070039}
40
41void mainboard_chromeos_acpi_generate(void)
42{
43 const struct cros_gpio *gpios;
44 size_t num;
45
46 gpios = variant_cros_gpios(&num);
47 chromeos_acpi_gpio_generate(gpios, num);
48}
Naresh G Solanki7b1b2462018-04-02 21:38:57 +053049
Aaron Durbin64031672018-04-21 14:45:32 -060050int __weak get_lid_switch(void)
Naresh G Solanki7b1b2462018-04-02 21:38:57 +053051{
52 return -1;
53}