blob: fd43334f5463be1cea009ea1c7f4c4c046ab0653 [file] [log] [blame]
Stefan Reinauer6651da32012-04-27 23:16:30 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Stefan Reinauer6651da32012-04-27 23:16:30 +020014 */
15
Aaron Durbin30b0c7a2016-07-13 13:01:13 -050016#include <arch/acpi.h>
Stefan Reinauer6651da32012-04-27 23:16:30 +020017#include <arch/io.h>
Stefan Reinauer6651da32012-04-27 23:16:30 +020018#include <cpu/x86/smm.h>
19#include <southbridge/intel/bd82x6x/nvs.h>
20#include <southbridge/intel/bd82x6x/pch.h>
21#include <southbridge/intel/bd82x6x/me.h>
22#include <northbridge/intel/sandybridge/sandybridge.h>
23#include <cpu/intel/model_206ax/model_206ax.h>
24
Stefan Reinauer6651da32012-04-27 23:16:30 +020025/*
26 * Change LED_POWER# (SIO GPIO 45) state based on sleep type.
27 * The IO address is hardcoded as we don't have device path in SMM.
28 */
29#define SIO_GPIO_BASE_SET4 (0x730 + 3)
30#define SIO_GPIO_BLINK_GPIO45 0x25
31void mainboard_smi_sleep(u8 slp_typ)
32{
33 u8 reg8;
34
35 switch (slp_typ) {
Aaron Durbin30b0c7a2016-07-13 13:01:13 -050036 case ACPI_S3:
37 case ACPI_S4:
Stefan Reinauer6651da32012-04-27 23:16:30 +020038 break;
39
Aaron Durbin30b0c7a2016-07-13 13:01:13 -050040 case ACPI_S5:
Stefan Reinauer6651da32012-04-27 23:16:30 +020041 /* Turn off LED */
42 reg8 = inb(SIO_GPIO_BASE_SET4);
43 reg8 |= (1 << 5);
44 outb(reg8, SIO_GPIO_BASE_SET4);
45 break;
46 }
47}