blob: 56938e7026d2bcf344f572d10bd070b061f0d877 [file] [log] [blame]
Tobias Diedrich7a952042017-12-03 10:09:28 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef DCP847SKE_SUPERIO_H
18#define DCP847SKE_SUPERIO_H
19
20#include <arch/io.h>
21
22#define NUVOTON_PORT 0x4e
23#define HWM_PORT 0x0a30
24#define GPIO_PORT 0x0a80
25
26#define SUPERIO_BANK(x) (0x0700 | x)
27#define SUPERIO_INITVAL(reg, data) ((reg << 8) | (data))
28#define HWM_BANK(x) (0x4e00 | x)
29#define HWM_INITVAL SUPERIO_INITVAL
30
31#define SUPERIO_UNLOCK do { \
32 outb(0x87, NUVOTON_PORT); \
33 outb(0x87, NUVOTON_PORT); \
34} while (0)
35
36#define SUPERIO_LOCK do { \
37 outb(0xaa, NUVOTON_PORT); \
38} while (0)
39
40#define SUPERIO_WRITE(reg, data) do { \
41 outb((reg), NUVOTON_PORT); \
42 outb((data), NUVOTON_PORT + 1); \
43} while (0)
44
45#define SUPERIO_WRITE_INITVAL(val) SUPERIO_WRITE((val) >> 8, (val) & 0xff)
46
47#define HWM_WRITE(reg, data) do { \
48 outb((reg), HWM_PORT + 5); \
49 outb((data), HWM_PORT + 6); \
50} while (0)
51
52#define HWM_WRITE_INITVAL(val) HWM_WRITE((val) >> 8, (val) & 0xff)
53
54#endif /* DCP847SKE_SUPERIO_H */