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Tobias Diedrich7a952042017-12-03 10:09:28 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright (C) 2014 Vladimir Serbinenko
6 * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; version 2 of
11 * the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <stdint.h>
Elyes HAOUASd07048a2019-04-21 20:17:11 +020020#include <cf9_reset.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020021#include <device/pci_ops.h>
Tobias Diedrich7a952042017-12-03 10:09:28 +010022#include <device/pci_def.h>
Tobias Diedrich7a952042017-12-03 10:09:28 +010023#include <console/console.h>
Elyes HAOUAS4ad14462018-06-16 18:29:33 +020024#include <northbridge/intel/sandybridge/raminit_native.h>
Patrick Rudolphda9302a2019-03-24 17:01:41 +010025#include <southbridge/intel/bd82x6x/pch.h>
Arthur Heymans58a89532018-06-12 22:58:19 +020026
Tobias Diedrich7a952042017-12-03 10:09:28 +010027#include "superio.h"
28#include "thermal.h"
29
Julius Wernercd49cce2019-03-05 16:53:33 -080030#if CONFIG(DISABLE_UART_ON_TESTPADS)
Tobias Diedrich7a952042017-12-03 10:09:28 +010031#define DEBUG_UART_EN 0
32#else
33#define DEBUG_UART_EN COMA_LPC_EN
34#endif
35
36void pch_enable_lpc(void)
37{
38 pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
39 CNF2_LPC_EN | DEBUG_UART_EN);
40 /* Decode SuperIO 0x0a00 */
41 pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);
42}
43
Nico Huberff4025c2018-01-14 12:34:43 +010044void mainboard_rcba_config(void)
Tobias Diedrich7a952042017-12-03 10:09:28 +010045{
46 /* Disable devices */
Nico Huberff4025c2018-01-14 12:34:43 +010047 RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI;
Tobias Diedrich7a952042017-12-03 10:09:28 +010048
Julius Wernercd49cce2019-03-05 16:53:33 -080049#if CONFIG(USE_NATIVE_RAMINIT)
Tobias Diedrich7a952042017-12-03 10:09:28 +010050 /* Enable Gigabit Ethernet */
51 if (RCBA32(BUC) & PCH_DISABLE_GBE) {
52 RCBA32(BUC) &= ~PCH_DISABLE_GBE;
53 /* Datasheet says clearing the bit requires a reset after */
54 printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n");
Elyes HAOUASd07048a2019-04-21 20:17:11 +020055 full_reset();
Tobias Diedrich7a952042017-12-03 10:09:28 +010056 }
57#endif
58
59 /* Set "mobile" bit in MCH (which makes sense layout-wise). */
60 /* Note sure if this has any effect at all though. */
61 MCHBAR32(0x0004) |= 0x00001000;
62 MCHBAR32(0x0104) |= 0x00001000;
63}
64
65void mainboard_early_init(int s3resume)
66{
67}
68
69static const u16 hwm_initvals[] = {
70 HWM_BANK(0),
71 HWM_INITVAL(0xae, 0x01), /* Enable PECI Agent0 */
72
73 HWM_BANK(7), /* PECI */
74 HWM_INITVAL(0x01, 0x95), /* Enable PECI */
75 HWM_INITVAL(0x03, 0x10), /* Enable Agent 0 */
76 /*
77 * PECI temperatures are negative, going up to 0.
78 * 0 represents the maximum allowable junction temperature, Tjmax.
79 * There is also Tcontrol, which is the temperature at which the
80 * system cooling should run at full speed.
81 * Since the NCT5577D fan control only supports positive values,
82 * Tbase0 is used as an offset.
83 */
84 HWM_INITVAL(0x09, CRITICAL_TEMPERATURE), /* Tbase0 */
85
86 HWM_BANK(2), /* CPUFAN control */
87 HWM_INITVAL(0x00, 0x0c), /* PECI Agent 0 as CPUFAN monitoring source */
88 HWM_INITVAL(0x01, 50), /* Target temperature */
89 HWM_INITVAL(0x02, 0x40), /* Enable Smart Fan IV mode */
90 HWM_INITVAL(0x03, 0x01), /* Step-up time */
91 HWM_INITVAL(0x04, 0x01), /* Step-down time */
92 HWM_INITVAL(0x05, 0x10), /* Stop PWM value */
93 HWM_INITVAL(0x06, 0x20), /* Start PWM value */
94 HWM_INITVAL(0x21, 45), /* Smart Fan IV Temp1 */
95 HWM_INITVAL(0x22, 46), /* Smart Fan IV Temp2 */
96 HWM_INITVAL(0x23, 47), /* Smart Fan IV Temp3 */
97 HWM_INITVAL(0x24, PASSIVE_TEMPERATURE), /* Smart Fan IV Temp4 */
98 HWM_INITVAL(0x27, 0x01), /* Smart Fan IV PWM1 */
99 HWM_INITVAL(0x28, 0x02), /* Smart Fan IV PWM2 */
100 HWM_INITVAL(0x29, 0x03), /* Smart Fan IV PWM3 */
101 HWM_INITVAL(0x2a, 0xff), /* Smart Fan IV PWM4 */
102 /* Smart Fan IV Critical temp */
103 HWM_INITVAL(0x35, CRITICAL_TEMPERATURE),
104 HWM_INITVAL(0x38, 3), /* Smart Fan IV Critical temp tolerance */
105 HWM_INITVAL(0x39, 0x81), /* Enable SYSTIN weight value */
106 HWM_INITVAL(0x3a, 1), /* SYSTIN temperature step */
107 HWM_INITVAL(0x3b, 2), /* SYSTIN step tolerance */
108 HWM_INITVAL(0x3c, 1), /* SYSTIN weight step */
109 HWM_INITVAL(0x3d, 40), /* SYSTIN temperature base */
110 HWM_INITVAL(0x3e, 0x00), /* SYSTIN fan duty base */
111
112 HWM_BANK(0),
113};
114
115static void hwm_init(void)
116{
117 /* Set up fan control */
118 for (int i = 0; i < ARRAY_SIZE(hwm_initvals); i++)
119 HWM_WRITE_INITVAL(hwm_initvals[i]);
120}
121
122static const u16 superio_initvals[] = {
123 /* Global config registers */
124 SUPERIO_INITVAL(0x1a, 0x02),
125 SUPERIO_INITVAL(0x1b, 0x6a),
126 SUPERIO_INITVAL(0x27, 0x80),
Julius Wernercd49cce2019-03-05 16:53:33 -0800127#if CONFIG(DISABLE_UART_ON_TESTPADS)
Tobias Diedrich7a952042017-12-03 10:09:28 +0100128 SUPERIO_INITVAL(0x2a, 0x80),
129#else
130 SUPERIO_INITVAL(0x2a, 0x00),
131#endif
132 SUPERIO_INITVAL(0x2c, 0x00),
133
134 SUPERIO_BANK(2), /* UART A */
135 SUPERIO_INITVAL(0x30, 0x01),
136 SUPERIO_INITVAL(0x60, 0x03),
137 SUPERIO_INITVAL(0x61, 0xf8),
138 SUPERIO_INITVAL(0x70, 0x04),
139
140 SUPERIO_BANK(7), /* GPIO config */
141 SUPERIO_INITVAL(0x30, 0x01),
142 SUPERIO_INITVAL(0xe0, 0xcf),
143 SUPERIO_INITVAL(0xe1, 0x0f),
144 SUPERIO_INITVAL(0xe4, 0xed),
145 SUPERIO_INITVAL(0xe5, 0x4d),
146 SUPERIO_INITVAL(0xec, 0x30),
147 SUPERIO_INITVAL(0xee, 0xff),
148
149 SUPERIO_BANK(8),
150 SUPERIO_INITVAL(0x30, 0x0a),
151 SUPERIO_INITVAL(0x60, GPIO_PORT >> 8),
152 SUPERIO_INITVAL(0x61, GPIO_PORT & 0xff),
153
154 SUPERIO_BANK(9),
155 SUPERIO_INITVAL(0x30, 0x8c),
156 SUPERIO_INITVAL(0xe1, 0x90),
157
158 SUPERIO_BANK(0xa),
159 SUPERIO_INITVAL(0xe4, 0x20),
160 SUPERIO_INITVAL(0xe6, 0x4c),
161
162 SUPERIO_BANK(0xb), /* HWM & LED */
163 SUPERIO_INITVAL(0x30, 0x01),
164 SUPERIO_INITVAL(0x60, HWM_PORT >> 8),
165 SUPERIO_INITVAL(0x61, HWM_PORT & 0xff),
166 SUPERIO_INITVAL(0xf7, 0x67),
167 SUPERIO_INITVAL(0xf8, 0x60),
168
169 SUPERIO_BANK(0x16),
170 SUPERIO_INITVAL(0x30, 0x00),
171};
172
173static void superio_init(void)
174{
175 SUPERIO_UNLOCK;
176 for (int i = 0; i < ARRAY_SIZE(superio_initvals); i++)
177 SUPERIO_WRITE_INITVAL(superio_initvals[i]);
178 SUPERIO_LOCK;
179}
180
181void mainboard_config_superio(void)
182{
183 superio_init();
184 hwm_init();
185}
186
187void mainboard_get_spd(spd_raw_data *spd, bool id_only)
188{
189 read_spd(&spd[0], 0x50, id_only);
190 read_spd(&spd[2], 0x51, id_only);
191}
192
193const struct southbridge_usb_port mainboard_usb_ports[] = {
194#define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin }
195#include "usb.h"
196};